Coverage-Driven RTL Assertion Generation with Formal Exploration and Neuro-Symbolic Refinement

In the invisible world of microchips, where billions of transistors switch on and off to power everything from smartphones to spacecraft, a single hidden error can cause a system to fail catastrophically. Engineers design these chips using a language called Register Transfer Level, or RTL, which describes how data moves between storage elements over time. To ensure these designs work correctly before they are built, verification experts write "assertions." Think of an assertion as a strict rule written into the design itself, a statement that says, "If this happens, then that must follow." If the chip ever violates this rule, the system raises an alarm, revealing a bug that might otherwise go unnoticed. For decades, writing these rules has been a slow, manual, and error-prone task, requiring engineers to guess which behaviors might go wrong and write specific checks for them. While computers have helped by mining existing design simulations to find patterns, these automated methods often miss the most dangerous scenarios simply because the random tests they rely on never stumble upon them.

A team of researchers at The Hong Kong University of Science and Technology (Guangzhou) has developed a new approach to solve this problem, calling their system NeuroAssertion. Instead of relying on random chance to find bugs, their method actively hunts for the hardest-to-reach behaviors in a chip design and then uses a combination of artificial intelligence and formal logic to write the necessary safety rules. The process begins by transforming the design to make it easier to see which parts are being tested. The researchers insert special markers into the code that track whether specific, difficult-to-trigger conditions have ever occurred. They then use a powerful mathematical engine, known as a model checker, to force the design to execute those rare conditions. This generates a set of highly specific test cases that expose behaviors random simulations would likely miss forever. These new, diverse traces provide a much richer foundation for the next step.

Once the system has these hard-to-find behaviors, it moves to the generation phase. It uses a technique called syntax-guided synthesis to create initial safety rules based on the observed data. However, the researchers recognized that this first pass is rarely perfect. To fix this, they introduced a refinement loop that acts like a rigorous editor. The system measures how well the current set of rules can detect changes in the design by injecting small, deliberate errors, known as mutants, into the code. If the rules fail to catch a mutant, the system knows exactly which behavior remains unchecked. It then calls upon a large language model to propose a new rule specifically designed to cover that gap. If the proposed rule is logically flawed, a second language model does not discard it; instead, it analyzes the error and constructs a specialized set of instructions, or a grammar, to guide a symbolic solver in repairing the rule. This creates a cycle where the system proposes, checks, and fixes assertions until they are both numerous and robust.

The results of this approach were tested on seven different chip designs, ranging from small arbitration circuits to complex processor cores. The new framework consistently outperformed the previous state-of-the-art method, known as SMART, which relies on a single pass of mining without this active refinement. In these experiments, NeuroAssertion generated roughly twice as many assertions as the older method. More importantly, the quality of these rules was significantly higher. When measured by their ability to detect injected errors, the new system achieved about twice the coverage of the traditional approach. On some specific benchmarks, the improvement was even more dramatic; for instance, on one processor component, the mutation coverage jumped from roughly six percent to over thirty-two percent. The researchers also compared their system against a direct approach where a large language model was asked to write rules without any of the formal checking or refinement steps. That direct method produced far fewer rules and failed to catch most of the potential errors, demonstrating that raw language generation alone is insufficient for this high-stakes task.

By treating assertion generation as a continuous loop of exploration and refinement rather than a one-time event, the researchers have shown that it is possible to automate the creation of high-quality safety rules for complex hardware. The system does not just guess; it actively seeks out the blind spots in a design and uses a partnership between neural networks and formal logic to fill them. This work suggests that the future of hardware verification lies in combining the pattern recognition of artificial intelligence with the rigorous certainty of mathematical proof, ensuring that the chips powering our world are as reliable as the engineers who design them.