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High-fidelity and robust controlled-Z gates for superconducting transmon qubits. I. Intrinsic errors and decoherence

This paper presents a comprehensive optimal-control framework for superconducting transmon qubits that achieves 12-ns high-fidelity controlled-Z gates with intrinsic errors suppressed to $2\times10^{-5}$ by systematically accounting for decoherence mechanisms and identifying dephasing sweet spots to enhance noise robustness.

Original authors: Chia-Hsien Huang, Hsi-Sheng Goan

Published 2026-10-22

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Chia-Hsien Huang, Hsi-Sheng Goan

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

The quest to build a machine that can solve problems beyond the reach of today's computers relies on a fragile foundation: the quantum bit, or qubit. Unlike the stable switches in a standard computer, these quantum units exist in a delicate state of probability, easily shattered by the slightest touch from their environment. To perform useful calculations, scientists must manipulate these qubits with extreme precision, flipping them from one state to another using gates that act like logical switches. However, these switches are prone to two main types of failure. First, the physical laws governing the qubits themselves can cause them to drift or leak energy, creating errors even in a perfect vacuum. Second, the real world is noisy; temperature fluctuations and electrical interference constantly bombard the system, scrambling the information before the calculation is finished. As researchers attempt to scale these systems from a handful of qubits to the thousands needed for practical use, the need for gates that are not only fast and accurate but also stubbornly resistant to this noise becomes critical. If every gate requires constant checking and recalibration, the machine will spend more time fixing itself than solving problems.

In a new study, researchers have developed a comprehensive strategy to build these resilient gates for superconducting transmon qubits, a leading type of quantum hardware. The team focused on the controlled-Z gate, a fundamental two-qubit operation, and sought to design a control signal that could execute the gate in record time while simultaneously suppressing both the internal errors of the system and the external noise that plagues it. By treating the design of the control signal as a complex optimization problem, they engineered a specific sequence of magnetic flux pulses that guide the qubits through their operation. This sequence is divided into two parts: a "pull-back" phase that rapidly moves the qubits to a favorable operating point, and a "fine-tune" phase that makes subtle adjustments to synchronize their behavior and cancel out errors. The result is a gate that operates in just 12 nanoseconds, a duration so brief it is nearly as fast as the theoretical speed limit for this type of hardware.

The researchers found that by carefully shaping these pulses, they could suppress the intrinsic errors of the gate to a level of 2 in 100,000. This is a remarkable achievement because it means the gate is almost perfect even before accounting for the messy reality of the laboratory environment. To address that reality, the team constructed detailed models of the noise sources, distinguishing between fast, random jitters from room-temperature electronics and slow, drifting noise that follows a specific pattern known as 1/f noise. They discovered that the qubits have "sweet spots"—specific operating frequencies where they are naturally less sensitive to these disturbances. By steering the qubits to these sweet spots during the gate operation, the team could drastically reduce the impact of the noise.

A key discovery in this work is the role of asymmetry in the design of the qubits themselves. The researchers showed that by intentionally making the two junctions inside a transmon qubit slightly different in size, they could tune the system to be robust against different types of noise. For instance, a specific degree of asymmetry allowed the gate to maintain high accuracy even when the fast noise from electronics was increased sevenfold or the slow drift noise was quadrupled. Other configurations offered even greater protection: one design could withstand a hundredfold increase in slow noise, while another could handle a tenfold increase in fast noise. This flexibility suggests that engineers can now tailor the physical properties of their qubits to match the specific noise environment of their laboratory, rather than fighting a losing battle against a generic background.

The study also addressed a practical hurdle often overlooked in theoretical designs: the limitations of the equipment used to generate the control signals. The machines that create these precise pulses have a finite bandwidth, which can distort the ideal waveforms and ruin the gate's performance. The researchers developed a method to "fine-tune" their optimized pulses to account for these distortions, effectively recovering the high-fidelity performance even when using standard commercial equipment. When they applied their best design to a system with the optimal asymmetry, the total error rate dropped to less than 5 in 10,000. While the remaining errors were primarily due to the natural energy loss of the qubits, the team noted that with future improvements in materials that could extend the qubit's lifespan, the error rate could potentially fall below the threshold required for fault-tolerant quantum computing.

This work establishes a unified framework that balances speed, accuracy, and robustness, offering a clear path forward for scaling up quantum processors. By combining rapid gate operations with noise-resistant designs and practical calibration techniques, the researchers have demonstrated that it is possible to build gates that remain reliable despite the inevitable variations and fluctuations found in large-scale hardware. The findings provide a blueprint for reducing the need for constant recalibration, a major bottleneck in current quantum systems, and suggest that the path to a functional, large-scale quantum computer may be paved with gates that are not just fast, but fundamentally tough.

Technical Summary: High-fidelity and robust controlled-Z gates for superconducting transmon qubits. I. Intrinsic errors and decoherence

Problem Statement
Fault-tolerant quantum computing requires quantum gates that simultaneously achieve short duration, high fidelity, and robustness to noise. As quantum processors scale, the exhaustive characterization and frequent recalibration of individual gates become impractical, creating an operational bottleneck. While superconducting transmon qubits have demonstrated high-fidelity two-qubit controlled-Z (CZ) gates, further improvements require a comprehensive understanding of the interplay between intrinsic Hamiltonian errors, realistic decoherence mechanisms (energy relaxation and dephasing), and systematic parameter uncertainties. Current challenges include developing control frameworks that account for multiple error sources under realistic experimental constraints (such as Arbitrary Waveform Generator bandwidth limitations) while maintaining robustness against noise fluctuations and device variations.

Methodology
The authors develop a unified optimal-control framework for directly coupled, frequency-tunable transmon qubits. The methodology integrates the following components:

Unified Optimal-Control Framework: The total gate infidelity is decomposed into a modular sum of contributions from intrinsic errors, energy relaxation, and dephasing. This allows the cost function to be tailored to dominant error mechanisms and extended to include additional sources.
Physics-Informed Pulse Design: The control flux pulse $\Phi(t)$ is constructed as a sum of a "Pull-Back-Pulse" ( $\Phi_{PBP}$ ) and a "Fine-Tune-Pulse" ( $\Phi_{FTP}$ ). $\Phi_{PBP}$ rapidly drives the system to a favorable operating point (sweet spot) and maintains it, while $\Phi_{FTP}$ provides local modulation to minimize the cost function. This structure ensures smooth transitions and facilitates efficient convergence.
Hierarchical Error Decomposition: Intrinsic errors are numerically decomposed into phase, swap, and leakage contributions. Leakage is further resolved into odd- and even-quanta paths (Qt-2 to Qt-6), and swap errors are separated into computational subspace rotations. This hierarchy guides simulation resource allocation.
Realistic Noise Modeling: Noise models are calibrated against published experimental Ramsey coherence measurements and CZ gate error budgets. These models capture fast dephasing (white noise from room-temperature control electronics) and slow dephasing ( $1/f$ flux noise). The models are validated by reproducing the experimentally measured qubit-frequency dependence of dephasing times $T_{\phi,1}$ and $T_{\phi,2}$ .
AWG-Filtering-Aware Fine-Tuning: A post-optimization procedure incorporates an experimentally relevant AWG filtering model (Gaussian filter) to account for waveform distortions caused by finite bandwidth, recovering gate performance in practical implementations.
Sweet-Spot Identification and Asymmetry Exploitation: The framework identifies "dephasing sweet spots" where the sensitivity to noise is minimized. It systematically explores transmon asymmetry (quantified by the Josephson energy ratio $a_{EJ} = E_{J1}/E_{J2}$ ) as a design parameter to access distinct noise-resilient operating regimes.

Key Contributions

Unified Framework: Integration of intrinsic Hamiltonian dynamics and calibrated decoherence models into a single gate-design process for simultaneous optimization of fidelity and robustness.
Pulse Engineering: Proposal of a specific pulse decomposition ( $\Phi_{PBP} + \Phi_{FTP}$ ) that establishes a favorable starting point for optimization, enabling the suppression of dominant errors.
Detailed Error Analysis: A numerical decomposition of intrinsic errors (phase, swap, leakage) that identifies dominant mechanisms and guides optimization objectives.
Experimental Constraint Handling: Development of a fine-tuning procedure that recovers gate fidelity despite AWG bandwidth limitations (e.g., 424.7 MHz cutoff).
Noise Modeling: Construction of realistic noise models for fast and slow dephasing, calibrated against experimental data, enabling quantitative prediction of gate performance.
Sweet-Spot and Asymmetry Strategies: Systematic identification of sweet spots for both fast and slow dephasing. The paper demonstrates that transmon asymmetry ( $a_{EJ}$ ) can be tuned to balance robustness against different noise types: strongly asymmetric transmons ( $a_{EJ} \approx 11.0$ ) suppress flux noise sensitivity, while weakly asymmetric transmons ( $a_{EJ} \approx 1.1$ ) suppress fast dephasing sensitivity.
Robustness Quantification: Quantification of tolerance margins, showing that optimized gates can maintain infidelity below $10^{-3}$ despite significant increases in noise strength (up to 90 $\times$ for slow dephasing in strongly asymmetric transmons and 10 $\times$ for fast dephasing in weakly asymmetric transmons).

Results

Gate Speed and Intrinsic Error: Using smooth, single-shot flux pulses, the authors achieve 12-ns CZ gates, close to the theoretical speed limit of 11.6 ns. Intrinsic errors are suppressed to the $2 \times 10^{-5}$ level.
Optimal Asymmetry: For transmons with an optimal asymmetry of $a_{EJ} = 1.31$ , operating near the joint fast- and slow-dephasing sweet spot yields a total gate infidelity of $4.66 \times 10^{-4}$ . This is predominantly limited by energy relaxation ( $4 \times 10^{-4}$ for $T_1 = 30$ $\mu$ s), with intrinsic errors at $2.46 \times 10^{-5}$ and total dephasing at $4.11 \times 10^{-5}$ .
Projected Performance: With state-of-the-art coherence times ( $T_1 = 360$ $\mu$ s, achievable with tantalum), the projected total infidelity decreases to $9.90 \times 10^{-5}$ . If room-temperature control electronics noise is eliminated, using strongly asymmetric transmons ( $a_{EJ} = 11.0$ ) yields a total infidelity of $5.22 \times 10^{-5}$ .
Robustness: The optimized gate maintains an infidelity below $10^{-3}$ even when fast-dephasing noise strength is increased sevenfold or slow-dephasing noise strength is increased fourfold relative to experimentally characterized levels.
Filtering Recovery: For a commercial AWG with a 424.7 MHz cutoff, the filtering effect initially increases intrinsic infidelity to $1.14 \times 10^{-2}$ . The proposed fine-tuning procedure reduces this to $2.05 \times 10^{-5}$ , effectively restoring the original performance.

Significance and Claims
The paper claims to establish an experimentally applicable framework for balancing gate speed, fidelity, and noise robustness. By reducing the need for precise characterization and frequent recalibration, this approach addresses a growing operational bottleneck for large-scale quantum hardware. The results demonstrate that transmon asymmetry serves as a tunable design parameter to tailor gate robustness to specific noise environments. The authors assert that their framework provides a foundation for extending these principles to more complex coupling architectures (e.g., tunable couplers, resonator-mediated coupling) and that the combination of near-speed-limit operation, sub- $10^{-3}$ infidelity, and multi-fold noise tolerance offers a pathway toward robust gate implementation in current and near-term superconducting hardware. The paper explicitly notes that while it addresses decoherence and intrinsic errors, the remaining critical challenge for fault tolerance—robustness against systematic parameter uncertainties—is addressed in a companion paper (Part II).

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