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FPGA-Based Real-Time Quantum Error Correction for Shor and Steane Codes

This paper presents a family of monolithic FPGA-based real-time quantum error correction decoders for Shor and Steane codes that achieve 300 million corrections per second with sub-microsecond latency, using minimal resources and demonstrating bit-exact correctness and logical error rates below the break-even threshold.

Original authors: Nasir Ali Nasir Ali

Published 2026-07-02

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Nasir Ali Nasir Ali

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to send a secret message across a very noisy room. If you just whisper the message once, the wind (noise) might change a word, and the person on the other side will hear the wrong thing. To fix this, you repeat the message three times: "Apple, Apple, Apple." If the wind changes the second one to "Aple," the listener can still guess the original word by taking a vote. This is the basic idea of Quantum Error Correction (QEC).

However, in the quantum world, the "wind" is incredibly fast and chaotic. The message (the quantum state) starts to fade away (decohere) in less than a millionth of a second. To save the message, you need a "guard" who listens to the noise, figures out what went wrong, and fixes it instantly—faster than the message can fade.

This paper describes a team that built a super-fast "guard" using a special kind of computer chip called an FPGA (Field-Programmable Gate Array). Here is how they did it, explained simply:

1. The Problem: The "Too Slow" Guard

Usually, computers use software (programs like Python) to act as these guards. But software is like a librarian who has to walk to a huge library, find a book, read it, and then walk back to tell you the answer. By the time the librarian returns, the quantum message has already faded away.

The Goal: The guard needs to make a decision in less than one microsecond (one-millionth of a second).
The Reality: Software is too slow. It's like trying to catch a bullet with a net made of spaghetti.

2. The Solution: The "Instant" Hardware Guard

The authors built their guard directly into the "wiring" of the chip itself, rather than writing a program for it. Think of it like building a dedicated, pre-laid train track from the input to the output. There are no stops, no traffic lights, and no waiting for a librarian.

The Chip: They used a powerful card called the Alveo U55C.
The Speed: Their guard can make 300 million corrections per second. That is thousands of times faster than what a standard computer or even a graphics card (GPU) can do for this specific task.

3. The Three "Prototypes" They Built

To prove their idea works, they built three different versions of this guard, getting progressively more complex:

The "Warm-Up" (3-Bit Repetition Code): This is the simplest version. It's like the "Apple, Apple, Apple" example. It's a small test to make sure the basic wiring works.
The "Shor Code" (9 Qubits): This is a more advanced guard that protects a single piece of information using nine "physical" pieces. It uses a Look-Up Table (like a giant cheat sheet) stored in the chip's memory. When it sees a specific pattern of noise, it instantly looks up the answer on the sheet and fixes it.
The "Steane Code" (7 Qubits): This is the most versatile guard. It's like a Swiss Army knife that can switch between three different ways of solving the problem on the fly:
1. The Cheat Sheet (LUT): Just like the Shor code, it looks up the answer.
2. The Puzzle Solver (MWPM): It mathematically calculates the best way to fix the error.
3. The Cluster Finder (Union-Find): It groups the errors together like a detective connecting dots to find the culprit.
- Surprise Finding: For these small codes, all three methods gave the exact same result. The simplest "Cheat Sheet" was just as good as the complex math solvers.

4. Why This Design is Special

Most high-speed systems need massive amounts of external memory (like a huge warehouse) to work fast. This design is unique because:

It's Self-Contained: The entire "guard" fits inside a tiny corner of the chip. It doesn't need to run to a warehouse to get its answers.
It's Tiny: The whole system uses less than 0.02% of the chip's total space.
The "Empty Room" Analogy: Imagine the chip is a massive stadium. The authors built their guard in a single seat. The rest of the stadium (99.98% of the space) is completely empty and available to do other things, like running a simulation of the quantum computer itself.

5. The Results

They tested their guards against every possible type of single error (like flipping a switch from 0 to 1).

Perfect Score: The guards caught and fixed every single error they were supposed to catch (27 out of 27 for the Shor code, 21 out of 21 for the Steane code).
Speed: They corrected errors in about 17 to 20 nanoseconds. To put that in perspective, light travels only about 6 meters in that time.
Efficiency: They proved that for these small, specific codes, you don't need a super-complex system. A simple, hard-wired circuit is all you need to beat the speed of light (in terms of data processing).

Summary

The paper shows that we don't need to wait for "perfect" quantum computers to start fixing their own errors. By using a specialized chip (FPGA) and designing a tiny, self-contained "guard" that lives directly on the hardware, we can correct errors fast enough to keep quantum information alive. It's like replacing a slow, walking librarian with a lightning-fast robot that lives inside the mailbox, ensuring the message never gets lost.

Technical Summary: FPGA-Based Real-Time Quantum Error Correction for Shor and Steane Codes

1. Problem Statement

Quantum error correction (QEC) for superconducting qubits requires a classical decoder to operate within the coherence budget of ancilla qubits, typically demanding a decision latency of under one microsecond. Current software-based decoders running on CPUs or GPUs achieve throughputs of only a few hundred thousand corrections per second, falling orders of magnitude short of the required real-time performance. Furthermore, high-latency software loops and GPU invocation overheads prevent the deployment of decoders in the tight control loops necessary for multi-round stabilizer experiments. While Field-Programmable Gate Arrays (FPGAs) offer deterministic, low-latency processing, there is a lack of complete, reproducible reference designs for distance-3 stabilizer codes that utilize high-level synthesis (HLS) and operate without relying on high-bandwidth memory (HBM), which is often reserved for quantum state simulation.

2. Methodology

The authors implemented, synthesized, and tested a family of three monolithic QEC decoder kernels using Vitis HLS targeting the Xilinx Alveo U55C FPGA (UltraScale+ XCVU55C). The design philosophy centers on a monolithic architecture where error injection, syndrome extraction, decoding, correction, and logical readout occur within a single function communicating exclusively via the AXI-Lite control bus. This approach avoids HBM access and DMA transfers, keeping the entire data path on-chip (registers and BRAM) to minimize latency.

The three kernels implemented are:

3-Bit Repetition Code (rep3): A pedagogical warm-up using a 2-bit syndrome and a 4-entry LUTRAM decoder.
Shor Code (shor): The nine-qubit [[9, 1, 3]] concatenated code. It utilizes an 8-bit syndrome and a 256-entry BRAM-backed Look-Up Table (LUT) decoder.
Steane Code (steane): The seven-qubit [[7, 1, 3]] CSS code. This kernel uniquely integrates three independently selectable decoder architectures within a single design, switchable at runtime via an AXI-Lite register:
- LUT: A direct BRAM lookup.
- Minimum-Weight Perfect Matching (MWPM): A combinational solver using priority encoders.
- Union-Find (UF): A cluster-based decoder using a single growth round on the Tanner graph.

The system operates at a 300 MHz clock frequency with an Initiation Interval (II) of 1, meaning one syndrome is processed per clock cycle. A bit-exact Python software mirror was developed for each hardware decoder to serve as a correctness oracle for host-side verification.

3. Key Contributions

The paper presents the following specific contributions:

First Complete HLS Implementations: Full Vitis HLS source code, synthesis reports, and timing data for Shor and Steane decoders targeting the Alveo U55C.
Monolithic AXI-Lite Architecture: A design achieving II=1 at 300 MHz (17–20 ns latency) with minimal resource usage (<800 LUT6, <2 BRAM18K, 0 DSPs), leaving >99.9% of the FPGA fabric available for co-hosting other tasks.
Multi-Decoder Kernel: A single Steane kernel capable of switching between LUT, MWPM, and UF decoding modes without re-synthesis or bitstream reloading.
Rigorous Verification: A 27/27 self-test for the Shor code and a 21/21 self-test for all three Steane modes against all single-qubit Pauli errors.
Monte Carlo Analysis: Threshold analysis over single-Pauli and IID-depolarising error models (10^5 shots per point), confirming logical error rates below the break-even point.
Scalability Roadmap: An analysis of LUT expansion versus syndrome width, quantifying the transition point where iterative decoders (like Belief Propagation) become necessary over LUT-based approaches.

4. Results

Timing and Latency: Both the Shor and Steane kernels met the 300 MHz timing constraint with substantial margin. The estimated critical-path delays were 2.318 ns (Shor) and 1.941 ns (Steane), well below the 3.33 ns target. End-to-end latency is approximately 17 ns for Shor and 20 ns for Steane.
Resource Utilization: The total resource footprint for all three kernels is negligible, utilizing less than 0.02% of the U55C's logic fabric. Specifically, the Steane kernel uses 744 LUT6s and 2 BRAM18K blocks.
Throughput: The FPGA kernel achieves 300 million corrections per second per compute unit. The authors note that up to 20 identical units could be instantiated on a single card, yielding an aggregate throughput of 6 × 10^9 corrections/s, which is three to four orders of magnitude higher than the syndrome production rate of current superconducting processors (~10^6 Hz).
Correctness: All 27 single-qubit Pauli errors for the Shor code and all 63 test cases (21 errors × 3 modes) for the Steane code passed verification with zero logical error flags.
Decoder Comparison: For the Steane code under IID-depolarising noise, the LUT, MWPM, and UF decoders produced statistically identical logical error rate curves. This confirms that for distance-3 codes with Hamming structure, the simplest LUT approach is as effective as more complex algorithms for weight-1 errors.
Logical Error Rates: The codes demonstrated below-threshold operation. The Shor code provided suppression for physical error rates $p \lesssim 0.08$ , and the Steane code for $p \lesssim 0.10$ .

5. Significance and Claims

The paper claims that for distance-3 stabilizer codes, the QEC decoder is fundamentally a classical circuit problem (XOR trees and BRAM lookups) rather than a quantum simulation problem. Consequently, it does not require the massive resources (HBM, DSPs) typically associated with quantum statevector simulation.

The authors emphasize that the monolithic AXI-Lite architecture is the key enabler for sub-20-nanosecond latency, as it eliminates off-chip memory access bottlenecks. The work provides a "drop-in" component for real-time control loops, demonstrating that the decoder itself is not the bottleneck for real-time deployment; rather, the challenge lies in system integration (latency of the control path from quantum hardware to FPGA and back).

The study modestly positions itself not as the creation of the world's fastest decoder (acknowledging ASIC surface-code decoders targeting <1 ns), but as a complete, reproducible reference design for distance-3 codes on commercial FPGA hardware. It validates that high-performance QEC decoding can be achieved with minimal hardware overhead, allowing the majority of the FPGA to be dedicated to the quantum statevector simulator or parallel QEC units.