Dynamic analogue iterative computing with memristors for real-time robotic autonomy

Technical Summary: Dynamic Analogue Iterative Computing with Memristors for Real-Time Robotic Autonomy

Problem Statement
Autonomous mobile robot (AMR) systems require real-time estimation, optimization, and control, which are fundamentally underpinned by dynamic matrix equations ($A(t)x(t)=b(t)$). Unlike static AI workloads, robotic tasks such as Simultaneous Localization and Mapping (SLAM) and path planning involve coefficient matrices that must be frequently updated in response to changing sensory inputs and environmental conditions. Current digital von Neumann architectures face a "memory wall" bottleneck, where moving data between separate memory and processing units incurs significant latency and energy overhead during iterative solving. While memristor-based analogue computing-in-memory (ACIM) offers a promising route to perform matrix-vector multiplication (MVM) in situ with high efficiency, its application to dynamic workloads is hindered by two primary challenges:

1. High Overhead of Matrix Updates: Accurate programming of memristor conductance typically requires iterative write-verify (WVP) processes to compensate for device stochasticity and variability. In dynamic scenarios, the energy and latency costs of these frequent updates can negate the computational benefits of analogue acceleration.
2. Precision in Dynamic Solving: Existing hybrid analogue-digital solvers suffer from data-transfer overheads due to repeated analogue-to-digital (AD) and digital-to-analogue (DA) conversions. Conversely, fully analogue solvers are sensitive to device variations and circuit imperfections, making high-precision solving difficult without addressing the specific demands of frequently changing matrices.

Methodology
The authors propose a memristor-based analogue iterative computing (mAIC) system designed to solve dynamic matrix equations efficiently and accurately. The system integrates two core innovations:

1. Analogue-Compensated Predictive One-Step Programming (AC-PoP):

   • To address the update bottleneck, the authors developed a scheme that replaces iterative WVP with a single predictive pulse followed by analogue compensation.
   • Using a pre-characterized predictive model of the memristor macro's response ($\Delta g = f(V)$), the system calculates a single programming pulse to drive the device toward a target conductance state.
   • Because predictive programming inevitably leaves residual errors due to device-to-device (D2D) and cycle-to-cycle (C2C) variations, the scheme employs a staged compensation mechanism. The residual error is passed to subsequent macros (or cycles) where it is corrected, allowing for accurate matrix updates without the latency of iterative verification.
   • Signed matrix updates are handled via a differential encoding scheme ($G_N = G_+ - G_-$), where updates are classified as magnitude-only or sign-reversing to optimize set/reset operations.

2. Continuous-Time Analogue Feedback Solver:

   • The mAIC system implements a fully analogue iterative architecture to solve the matrix equations directly in the analogue domain.
   • The matrix equation is converted into an iterative form ($x_{i+1} = Bx_i + f$). The iteration matrix $B$ is realized using multiple conductance matrices scaled by transimpedance amplifiers (TIAs).
   • The system operates as a closed-loop feedback circuit where the output of the MVM is summed with the vector term $f$ and fed back as the input for the next iteration. This allows for continuous-time convergence without repeated AD/DA conversions.
   • The hardware platform utilizes foundry-fabricated 1-Kb 1T1R (one-transistor-one-resistor) TaOx memristor macros integrated with CMOS circuitry, including microcontrollers, transfer gates, and analogue adders.

Key Contributions

• AC-PoP Scheme: A novel programming strategy that enables accurate, low-latency, and energy-efficient dynamic matrix updates on imperfect memristor devices, reducing the need for iterative write-verify cycles.
• Integrated mAIC System: A hardware demonstration combining AC-PoP with a continuous-time analogue solver, achieving software-comparable accuracy for dynamic workloads.
• Scalability Analysis: An evaluation of a block-wise mapping strategy for large-scale sparse matrix equations, demonstrating how the system can handle large-scale SLAM problems while mitigating circuit non-idealities like IR-drop.

Results
The system was validated using foundry-fabricated memristor macros on both simulated and real-world robotic tasks:

• Update Efficiency: Compared to conventional WVP, the AC-PoP scheme reduced matrix update energy by 101-fold and latency by 345-fold while maintaining comparable update accuracy.
• SLAM Backend Optimization: In a SLAM localization task derived from the KITTI dataset, the mAIC system achieved a relative conductance mapping error of 0.09% (at 3 compensation cycles) and a mean solution error of $4.57 \times 10^{-4}$. The reconstructed trajectory had a translation error of 0.49%, comparable to the 0.39% error of a CPU-based direct solver.
• Real-World Path Planning: In a physical mobile robot experiment involving dynamic replanning in a changing environment, the mAIC system achieved a 4.4-fold reduction in processing latency and a 627.9-fold reduction in energy consumption compared to an NVIDIA Jetson platform. The system maintained an average absolute solution error of approximately $1.85 \times 10^{-3}$ over 40 replanning steps.
• Scalability: SPICE simulations of large-scale SLAM tasks using a row-block mapping strategy showed that the system could converge within 19.8 μs per solve with minimal accuracy loss relative to digital references, even as matrix scales increased.

Significance and Claims
The paper claims that this work advances memristor-based computing from a paradigm of predominantly static matrix acceleration toward accurate and dynamically reconfigurable analogue computing. By solving the critical bottleneck of frequent matrix updates through the AC-PoP scheme, the authors demonstrate that memristor-based ACIM can support real-time robotic autonomy with energy and latency profiles superior to state-of-the-art digital edge processors.

The authors position this capability as a foundation for future edge intelligence, suggesting that efficient dynamic updates in memristive hardware could enable online adaptation, in situ learning, and continuous model evolution in response to physical environments. The work does not claim to solve all challenges of memristor computing but specifically addresses the transition from static to dynamic workloads, providing a feasible path toward fully integrated mAIC chips for complex AMR applications.