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Fast-Switching Monolayer MoSiGeN4 Transistors: Device Performance at Sub-5 nm High-Performance Nodes

This study demonstrates that double-gated monolayer Janus MoSiGeN4 transistors, evaluated via first-principles simulations, achieve high-performance and energy-efficient operation at sub-5-nm gate lengths that significantly exceed the 2028 International Technology Roadmap for Semiconductors targets, particularly when optimized with source/drain underlap.

Original authors: Himel Kundu Utsha, Md. Sabbir Ahmed, Arpa Roy Dastider, Md. Kawsar Alam

Published 2026-09-07

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CC BY 4.0

Original authors: Himel Kundu Utsha, Md. Sabbir Ahmed, Arpa Roy Dastider, Md. Kawsar Alam

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

The relentless drive to make computers faster and more efficient has long relied on shrinking the tiny switches inside them, known as transistors. For decades, engineers have successfully squeezed more of these switches onto a single chip by making them smaller, a trend that has powered the digital revolution. However, as these switches approach the size of a few nanometers—mere billionths of a meter—the standard materials used to build them, primarily silicon, begin to fail. At this microscopic scale, silicon struggles to hold its electrical charge, leading to leaks and a loss of control that prevents the switches from turning fully on or off. To keep progress alive, scientists are looking beyond silicon to a new class of materials that are only a single layer of atoms thick. These two-dimensional materials offer a way to maintain tight control over electricity even when the switches become incredibly small, potentially allowing the next generation of electronics to continue shrinking without hitting a dead end.

In this search for a successor to silicon, researchers from the Bangladesh University of Engineering and Technology have turned their attention to a newly predicted material called monolayer MoSiGeN4. This substance belongs to a family of crystals that are just one atom thick, but with a special twist: the atoms are arranged in an asymmetrical pattern, with different types of atoms on the top and bottom layers. This structural imbalance creates a built-in electric field that helps the material control the flow of electrons more effectively than its symmetrical cousins. The researchers set out to test whether this specific material could serve as the channel—the path through which electricity flows—in a transistor designed for the ultra-small gate lengths expected in the near future. Using powerful computer simulations based on the fundamental laws of quantum mechanics, they modeled a double-gated transistor, where the flow of current is controlled by metal gates on both the top and bottom of the material, and examined how it performed as they shrunk the gate length down to just two nanometers.

The team discovered that the material behaves exceptionally well when the gate length is four nanometers or larger, meeting the strict performance targets set by the semiconductor industry for high-speed devices. In these simulations, the transistor could switch on and off rapidly while consuming very little energy, outperforming the requirements for the year 2028. However, when they pushed the gate length down to three or two nanometers without any modification, the device began to struggle. The electrons started to leak through the switch even when it was supposed to be off, a problem known as short-channel effects, which caused the performance to drop below the necessary standards. To solve this, the researchers introduced a small design feature called an underlap, which is a slight gap between the gate and the source or drain contacts. This extra space acts like a buffer, giving the gate more control over the channel and preventing the electrons from tunneling through when they shouldn't.

With this underlap structure in place, the simulations showed a dramatic recovery in performance. The transistor could once again meet the industry's high-performance targets even at a gate length of just two nanometers. In fact, the device not only met the targets but exceeded them, delivering a current that was significantly higher than required while maintaining a sharp ability to switch between on and off states. Perhaps most impressive was the speed and energy efficiency of the device. The simulations indicated that the time it takes for the transistor to switch was incredibly fast, measured in fractions of a picosecond, and the energy used for each switch was far lower than what is currently projected as the limit for future technology. The material's unique asymmetry, which creates that helpful internal electric field, appeared to be the key factor allowing it to maintain such tight control over the electrons at these extreme scales.

The study also placed this new material side-by-side with other promising two-dimensional candidates, such as molybdenum disulfide and various other layered compounds. In these comparisons, the MoSiGeN4 transistor consistently ranked at the top, showing a better balance of high current, low energy use, and fast switching speeds than the other materials tested at the same gate length. The researchers noted that while these results are currently based on computer models and have not yet been built in a laboratory, the theoretical performance is so strong that it warrants serious experimental investigation. If these simulations hold true in the real world, monolayer MoSiGeN4 could become a cornerstone for the next generation of ultra-fast, energy-efficient electronics, allowing devices to continue shrinking well beyond the limits of current silicon technology. The findings suggest that by leveraging the unique properties of this Janus-structured material, engineers may have found a viable path to keep the pace of technological advancement moving forward.

Technical Summary: Fast-Switching Monolayer MoSiGeN4 Transistors

Problem Statement
The continuous miniaturization of silicon-based transistors is approaching fundamental physical limits, including short-channel effects (SCEs), drain-induced barrier lowering, and increased gate leakage. While advanced architectures like FinFETs and GAAFETs have extended CMOS scaling, they cannot fully eliminate the constraints imposed by silicon's inability to scale below a few nanometers without severe performance degradation. Two-dimensional (2D) semiconductors offer a potential solution due to their atomically thin bodies and dangling-bond-free surfaces, which enable superior electrostatic control. However, existing 2D candidates have limitations: graphene lacks a bandgap, Transition Metal Dichalcogenides (TMDs) like MoS2 suffer from low carrier mobility, and Black Phosphorus (BP) lacks environmental stability. Recently, the MA2N4 family (e.g., MoSi2N4) has shown promise, but n-type devices in this family fail to meet high-performance (HP) targets below 5 nm, and other variants like WSi2N4 are limited to gate lengths ≥3 nm. There is a need for a 2D channel material that supports high-speed, energy-efficient operation at sub-5 nm gate lengths, specifically for n-type logic.

Methodology
This study investigates the performance of a double-gated (DG) n-type field-effect transistor (FET) utilizing a monolayer Janus MoSiGeN4 channel. The research employs a computational framework combining first-principles Density Functional Theory (DFT) with the Non-Equilibrium Green's Function (NEGF) formalism.

Device Architecture: A symmetric DG structure was modeled with a central intrinsic channel, heavily n-doped source/drain regions (electrostatic doping at 1 × 10¹³ cm⁻²), and SiO₂ gate dielectrics (0.41 nm thickness, EOT = 0.41 nm).
Transport Directions: Performance was evaluated along both armchair and zigzag transport directions.
Simulation Parameters: Calculations were performed using the Quantum Atomistic Tool Kit (ATK) 2019. The study utilized the GGA-PBE functional with Spin-Orbit Coupling (SOC) to account for the transition metal.
Scaling Analysis: Device performance was analyzed across gate lengths ( $L_g$ ) ranging from 2 nm to 5 nm. To address short-channel effects at smaller nodes, the study introduced source/drain underlap (UL) lengths ( $UL$ ) ranging from 0 to 3 nm.
Metrics: Key performance indicators included on-state current ( $I_{on}$ ), off-state current ( $I_{off}$ ), subthreshold swing (SS), intrinsic delay ( $\tau$ ), and power-delay product (PDP). These were benchmarked against the International Technology Roadmap for Semiconductors (ITRS) 2028 HP targets.

Key Contributions and Results
The study demonstrates that monolayer MoSiGeN4 is a viable channel material for sub-5 nm high-performance logic, with performance metrics significantly exceeding roadmap requirements.

Material Properties: The optimized monolayer MoSiGeN4 exhibits an indirect bandgap of 1.35 eV. The electron effective mass is calculated at 0.374 $m_0$ (along both armchair and zigzag directions), indicating significantly higher electron mobility compared to hole mobility. The Janus structure induces an out-of-plane polarization and built-in electric field, enhancing electrostatic gate control.
Scaling Without Underlap: Without underlap, the device meets ITRS 2028 HP targets ( $I_{on} \ge 900$ µA/µm, $SS < 100$ mV/dec) down to a 4 nm gate length. At 5 nm and 4 nm, $I_{on}$ reached 1064 µA/µm and 1042 µA/µm, respectively. However, at 3 nm and 2 nm, performance degraded due to source-to-drain tunneling, with $I_{on}$ dropping to 597 µA/µm and 99 µA/µm, and SS worsening to 141 mV/dec and 220 mV/dec.
Impact of Underlap (UL): Introducing a modest underlap restored electrostatic control and suppressed tunneling.
- For $L_g = 3$ nm, a 1 nm UL increased $I_{on}$ from 597 µA/µm to 1013 µA/µm, meeting the ITRS target.
- For $L_g = 2$ nm, a 2 nm UL increased $I_{on}$ from 99 µA/µm to 910 µA/µm, satisfying the HP requirements.
- The optimal UL length was found to be 2 nm for the 2 nm gate device; increasing UL beyond this reduced $I_{on}$ due to weaker gate controllability in the extended underlap region.
Delay and Power Efficiency: The intrinsic delay ( $\tau$ $τ$ ) and power-delay product (PDP) remained far below ITRS limits across all studied gate lengths.
- The lowest delay achieved was 0.006 ps (at $L_g = 2$ nm with 3 nm UL), compared to the 2028 target of 0.423 ps.
- The PDP ranged from 0.004 fJ/µm to 0.010 fJ/µm, well below the 0.240 fJ/µm target.
Comparative Performance: When benchmarked against other monolayer 2D materials (e.g., MoS2, InSe, Silicene, MoSi2N4) at a 3 nm gate length, MoSiGeN4 demonstrated superior performance, combining a high $I_{on}$ (1317 µA/µm) with a low SS (86 mV/dec) and the lowest PDP (0.005 fJ/µm) among the compared candidates.

Significance
The paper claims that this work represents the first demonstration of such high switching speeds and energy efficiency potential in MoSiGeN4. The findings establish the double-gated monolayer MoSiGeN4 FET as a compelling candidate for next-generation logic applications beyond the 5-nm node. Specifically, the study highlights that the material's intrinsic properties, combined with a simple underlap engineering strategy, allow it to satisfy rigorous ITRS HP targets down to a 2 nm gate length. The authors conclude that MoSiGeN4 offers a pathway to high-speed, energy-efficient transistors that substantially exceed current roadmap requirements, warranting further experimental investigation to validate these theoretical predictions.

Technical Summary: Fast-Switching Monolayer MoSiGeN4 Transistors

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