⚡ electrical engineering

Quantitative Analysis of the Synchronization Stability Region of Grid-Connected Converters During Fault Ride-Through Considering LVRT Characteristics

This paper quantitatively characterizes the synchronization stability region of grid-connected converters during fault ride-through under weak-grid conditions by integrating quasi-steady-state, transient, and small-signal stability analyses based on low-voltage ride-through (LVRT) control logic, with the resulting stability boundaries validated through hardware-in-the-loop simulations.

Original authors: Fei Li, Huanhuan Chen, Longchao Guo, Qiang Chen, Xing Zhang

Published 2026-09-28

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CC BY 4.0

Original authors: Fei Li, Huanhuan Chen, Longchao Guo, Qiang Chen, Xing Zhang

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Modern power systems are undergoing a profound transformation, shifting from massive, spinning generators to a landscape dominated by renewable energy sources like wind and solar. These sources do not generate electricity directly; instead, they rely on sophisticated electronic devices called converters to translate their power into a form the grid can use. Think of these converters as the translators that allow the new, variable energy of the sun and wind to speak the same language as the traditional grid. However, this shift has made the entire system more sensitive. When the grid encounters a sudden disturbance, such as a short circuit caused by a fallen tree or a lightning strike, the voltage at the connection point can drop sharply. For a converter to survive this event without disconnecting and causing a blackout, it must ride through the low voltage, maintaining its connection and helping to stabilize the grid. This ability is known as low-voltage ride-through, and it is a critical requirement for keeping the lights on in a renewable-heavy world.

The challenge lies in the fact that these electronic devices must stay perfectly synchronized with the rhythm of the grid. If the voltage drops too low or the grid becomes too weak, the converter can lose its place in this rhythm, much like a runner stumbling and falling out of step with a marching band. When this happens, the device disconnects, and if enough devices fall out of step at once, the result can be a widespread power failure. Engineers have long tried to map out the safe operating limits for these converters, but existing methods often fail to account for the complex, nonlinear behavior that occurs specifically during these voltage dips. They struggle to predict exactly how deep a voltage drop a converter can tolerate before it loses synchronization, especially when the strength of the grid itself is changing.

A team of researchers from Hefei University of Technology and Sungrow Power Supply Co., Ltd. has tackled this problem by creating a detailed, three-dimensional map of safety for grid-connected converters during faults. Instead of looking at the system as a single, static state, they analyzed the journey a converter takes from before a fault occurs, through the moment of the voltage drop, and into the new, altered state afterward. They focused on three specific ways a converter can fail to stay synchronized. First, there is the question of whether a stable state even exists after the fault; if the voltage drops too low and the grid is too weak, the mathematical conditions for a stable connection simply disappear. Second, even if a stable state exists, the converter might fail to reach it, getting lost in a chaotic transition between the old and new conditions. Third, the converter might reach a new state but remain unstable there, wobbling uncontrollably due to small internal fluctuations.

To solve this, the researchers developed a unified approach that treats the grid's electrical strength and the depth of the voltage drop as the two main variables. They built a model that incorporates the specific logic converters use during a fault, which involves injecting reactive current to support the grid while limiting the total current to protect the hardware. By simulating the system under thousands of different combinations of voltage drops and grid strengths, they were able to draw precise boundaries. They found that the safe operating region is not a simple shape but a complex area defined by the intersection of these three stability limits. In many cases, the most restrictive limit is not whether a stable state exists, but whether the converter can successfully transition to it without losing its rhythm, or whether it will remain stable once it arrives.

The researchers confirmed their theoretical maps using a hardware-in-the-loop simulation, a technique where a real physical controller is connected to a computer that simulates the rest of the power system. This setup allowed them to test the boundaries in a realistic environment without risking damage to actual equipment. They selected specific scenarios where the voltage dropped to very low levels, such as 12 percent or 25 percent of the normal value, and tested the converters at the very edge of the predicted safe zones. In the simulations, when the grid strength was just below their calculated limit, the converters lost synchronization, with their frequency and power angles spiraling out of control. When the grid strength was just above the limit, the converters successfully rode through the fault and returned to stable operation. These results validated that their three-part analysis accurately predicts the point of failure.

The study reveals that the ability of a converter to survive a fault is highly dependent on the specific combination of how weak the grid becomes and how deep the voltage sag is. It also highlights that a converter can be in a situation where a stable state theoretically exists, yet the device still fails to reach it because the path there is too turbulent. Furthermore, the researchers discovered that even when a converter successfully transitions to a new state, it can enter a region of small-signal instability, where it begins to oscillate and eventually loses connection, a phenomenon driven by the complex interaction between the control loops and the current limits. This work provides a quantitative tool for engineers to design more robust systems, ensuring that as the world moves toward a grid powered by renewables, the electronic translators remain synchronized and reliable even when the grid is under the most severe stress.

Technical Summary: Quantitative Analysis of the Synchronization Stability Region of Grid-Connected Converters During Fault Ride-Through Considering LVRT Characteristics

Problem Statement
In the context of "dual-high" power systems characterized by high renewable penetration and power-electronic dominance, grid-connected converters are increasingly sensitive to external network parameters. During short-circuit faults, both the terminal voltage and the equivalent grid admittance can change abruptly. While steady-state stability boundaries (often characterized by the Short-Circuit Ratio, SCR) are well-studied, existing methods are inadequate for quantitatively characterizing synchronization stability boundaries under large disturbances, specifically voltage sags.

Current literature often addresses specific instability mechanisms in isolation:

Quasi-static instability: Existing criteria for equilibrium existence often assume prescribed current references, failing to account for the feedback loop where Low-Voltage Ride-Through (LVRT) control logic adjusts current references based on Point of Common Coupling (PCC) voltage, which in turn alters the grid impedance voltage drop.
Transient instability: Methods like the Equal Area Criterion (EAC) often neglect damping or assume constant damping, whereas Phase-Locked Loop (PLL) damping varies with system state. Furthermore, existing phase-trajectory studies typically assess prescribed fault conditions rather than mapping the redistribution of LVRT currents and post-fault voltages to a critical grid-admittance boundary.
Small-signal instability: Under LVRT conditions, strong coupling occurs between PCC-voltage-dependent current references, current limiting, PLL dynamics, and LCL filters. Standard reduced-order models often fail to capture these high-order interactions necessary to determine stability boundaries during faults.

Methodology
The paper proposes a systematic approach to construct a comprehensive synchronization stability region using the per-unit magnitude of the post-fault grid admittance ( $|Y_{g,p.u.}|$ ) and the post-fault grid voltage ( $V_{gf,p.u.}$ ) as unified quantitative indices. The analysis is conducted from three complementary perspectives:

Quasi-Static Stability (Equilibrium Existence):
- The authors derive a criterion for the existence of post-disturbance quasi-steady-state equilibrium points.
- By integrating LVRT control logic (where reactive current is prioritized and active current is reduced based on voltage sag depth) with the grid-side voltage-vector relationship, the intermediate fault-current reference variable is eliminated.
- A constraint equation is established to determine the critical grid-admittance boundary required for an operating point to exist under various voltage-sag depths.
Transient Stability (Transition Dynamics):
- A second-order nonlinear transient model is established, considering LVRT current references and post-fault grid parameters. The current control loop is neglected due to its faster bandwidth compared to the PLL.
- The model is analogous to a synchronous machine, defining equivalent inertia, mechanical torque, electromagnetic torque, and damping.
- A two-parameter scan of the sagged grid voltage and grid-admittance magnitude is performed. Phase-trajectory analysis is used to identify the boundary where trajectories diverge from the post-fault stable equilibrium point, indicating transient loss of synchronism.
Small-Signal Stability (Local Stability):
- A high-order (11th-order) small-signal state-space model is developed. This model explicitly accounts for LVRT current regulation, current limiting, multi-loop coupling, and the low-pass filtering of the PCC voltage used for fault detection.
- A piecewise modeling approach is adopted: one Jacobian matrix ( $B_1$ ) applies when current references are below the limit, and another ( $B_2$ ) applies when the limit is reached.
- Eigenvalue analysis of these Jacobian matrices over the operating space determines the small-signal stability boundary.
Validation:
- The theoretical boundaries are integrated to form a comprehensive stability region.
- Hardware-in-the-Loop (HIL) simulations using an RT-LAB platform and RTU-BOX are conducted under multiple operating conditions (specifically at $V_{gf,p.u.} = 0.12$ and $0.25$ p.u.) to validate the theoretical boundaries.

Key Results

Integrated Stability Region: The study successfully constructs a synchronization stability region defined by the intersection of the quasi-static, transient, and small-signal stability boundaries.
Dominant Constraints: Under the tested control parameters, the quasi-static stability boundary (existence of an equilibrium point) lies below the other two boundaries. Consequently, the overall stability region is primarily determined by the transient stability boundary and the small-signal stability boundary.
Nonlinear Characteristics: The small-signal stability boundary exhibits pronounced nonlinear and locally discontinuous characteristics. The system can transition from "stable" to "unstable" and back to "stable" as grid admittance varies, a phenomenon attributed to the switching of the Jacobian matrix when current limits are reached.
Verification: HIL simulations confirmed that:
- At low grid admittance ( $|Y_{g,p.u.}| = 4$ ) and deep voltage sag ($0.12$ p.u.), the system experiences transient instability despite the existence of a stable post-fault equilibrium.
- At higher grid admittance and the same voltage sag ($0.12$ p.u.), the system exhibits non-monotonic stability behavior: operating points $p13$ ( $|Y_{g,p.u.}| = 6.74$ ) and $p15$ ( $|Y_{g,p.u.}| = 6.4$ ) remain stable, whereas the intermediate point $p14$ ( $|Y_{g,p.u.}| = 6.65$ ) falls within an unstable region and exhibits small-signal instability.
- At moderate voltage sag ($0.25$ p.u.), the transient stability boundary is the limiting factor.

Significance and Claims
The paper claims to provide a quantitative framework for assessing the synchronization stability of grid-connected converters during fault ride-through, addressing the gap where existing methods cannot characterize critical stability boundaries across different voltage-sag depths and grid strengths.

Key contributions include:

The derivation of a quasi-static stability criterion that inherently accounts for the feedback between LVRT current references and PCC voltage.
The establishment of a unified stability region that simultaneously considers the existence of equilibrium points, the transition dynamics between pre- and post-fault states, and the local stability of the post-fault operating point.
The demonstration that even when a post-fault equilibrium exists and the transition is transiently stable, small-signal instability can still occur under specific grid-admittance conditions due to the complex coupling of control loops and current limiting.

The authors conclude that the transient synchronization stability capability decreases as grid admittance decreases and voltage-sag severity increases, and that the stability region is jointly determined by the transient and small-signal boundaries, both of which are influenced by PLL parameters.

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