A framework of partial error correction for intermediate-scale quantum computers

Technical Summary: A Framework of Partial Error Correction for Intermediate-Scale Quantum Computers

Problem Statement
As quantum hardware transitions from the Noisy Intermediate-Scale Quantum (NISQ) era toward fully fault-tolerant systems, a critical challenge arises: how to optimally allocate limited resources between computational tasks and error correction. Current NISQ algorithms rely on physical qubits and noise mitigation techniques, while fault-tolerant approaches require vast resources for full error correction. Recent hardware milestones have enabled the creation of a small number of high-quality, error-corrected ("clean") qubits. However, the number of such qubits is insufficient to run large-scale computations entirely on error-corrected registers. The paper addresses the gap between these regimes by investigating a "partial error correction" framework, where a fraction of qubits are error-corrected and coupled to a larger collection of noisy, non-corrected qubits. The central question is whether this hybrid architecture can provide a computational advantage over fully noisy systems.

Methodology
The authors develop a concrete theoretical and numerical framework for interacting clean and noisy qubits:

1. Logical Gate Construction: The paper proposes a method to implement universal two-qubit gates between clean and noisy registers. For stabilizer codes (e.g., surface codes, color codes) that admit transversal logical Pauli operators, the authors define a logical CNOT gate ($\hat{\text{CNOT}}$) between a noisy qubit and an encoded clean qubit. This gate is constructed using exactly $w$ physical two-qubit gates, where $w$ is the weight of the logical Pauli operator. While this construction allows for universal Clifford operations, the authors note it is not fault-tolerant, as errors on the noisy register can propagate to multiple clean registers.
2. Noise Modeling: The authors introduce a heuristic noise model for the hybrid system. They categorize logical gates into three types based on their physical implementation and associated error rates:
   • Type-d: Gates between two noisy qubits (error rate $\epsilon_d$).
   • Type-c: Gates between two clean qubits (error rate $\epsilon_c < \epsilon_d$ due to QEC).
   • Type-b: Gates on the boundary between clean and noisy registers (error rates $\epsilon_b, \epsilon_b'$). The model posits that $\epsilon_b$ is significantly higher than $\epsilon_d$ because the implementation requires multiple physical gates acting on the noisy qubit, and $\epsilon_b'$ is higher than $\epsilon_c$ due to error propagation from the noisy side.
3. Analytic Analysis: Using a random brick-layered circuit model with local depolarizing noise, the authors derive a lower bound on the trace distance between the circuit output and the maximally mixed state. This analysis investigates how the concentration of the output state (a proxy for computational utility) scales with circuit depth and the number of clean qubits.
4. Numerical Simulations: The authors perform extensive numerical simulations using a stabilizer simulator and the Steane code ($[[7,1,3]]$). They employ randomized benchmarking to estimate logical error rates for the hybrid gates and simulate random mirrored Clifford circuits of varying depths and sizes. The simulations incorporate realistic noise models, including single-qubit and two-qubit depolarizing noise, state preparation and measurement (SPAM) errors, and idling noise, calibrated to current trapped-ion hardware (e.g., Quantinuum H2).

Key Contributions and Results

• Threshold Behavior: The primary finding is the existence of a threshold number of clean qubits ($n_{\text{threshold}}$). The paper demonstrates that partial error correction only yields a performance advantage over a fully noisy system when the number of clean qubits exceeds this threshold. Below the threshold, the high error rates associated with the clean-noisy couplings ($\hat{\text{CNOT}}$) degrade the system's performance more than a fully noisy setup.
• Analytic Scaling: Theorem 2 provides an analytic lower bound showing that the decay of the trace distance to the maximally mixed state is mitigated by the fraction of clean qubits but penalized by the number of clean-noisy boundaries. The advantage is realized only when the number of clean qubits $n_c$ satisfies a specific inequality dependent on the error rates ($\epsilon_c, \epsilon_d, \epsilon_b$) and the number of boundaries. Crucially, this threshold is independent of the total qubit count $n$ in the absence of idling noise, but depends on the coupling structure.
• Numerical Verification: Simulations confirm the analytic predictions. For a system with $n=20$ qubits, the authors observe that using a small number of clean qubits (e.g., $n_c=2, 4$) results in lower fidelity than a fully noisy system ($n_c=0$). However, as $n_c$ increases (e.g., $n_c=7$), the fidelity surpasses the fully noisy case.
• Impact of Idling Noise: The study reveals that idling noise significantly affects the threshold. As the ratio of idling noise to gate noise ($\epsilon_I/\epsilon_{\text{CNOT}}$) increases, the required number of clean qubits ($n_{\text{threshold}}$) grows approximately linearly with the total system size $n$. This is attributed to the increased circuit depth required for error correction rounds on clean registers, leading to longer idling times for the noisy registers.
• Error Detection vs. Correction: The framework is also tested under Quantum Error Detection (QED) regimes with higher error rates ($\epsilon_{\text{CNOT}} \approx 10^{-3}$). Even in this regime, partial error correction (or detection) outperforms fully noisy systems, though it comes with a lower post-selection probability (higher shot overhead).

Significance and Claims
The paper claims to provide the first concrete framework and evidence that performing error correction on a fraction of the logical space can yield a computational advantage. The significance lies in offering a practical pathway for the transitional era between NISQ and fault tolerance:

• Resource Optimization: It suggests that rather than waiting for enough resources to fully error-correct a large system, one can achieve quantum advantage sooner by protecting a subset of qubits, provided the system size and coupling strategy are optimized to pass the clean-qubit threshold.
• Mitigation of Noise Concentration: The framework demonstrates that partial error correction can slow the concentration of circuit outputs to the "useless" uniform distribution compared to fully noisy circuits, provided the number of clean qubits is sufficient to overcome the penalty of boundary couplings.
• Practical Applicability: The results are grounded in realistic hardware constraints, including specific noise models for trapped-ion devices and the overhead of the Steane code. The authors emphasize that this approach is particularly relevant for low-depth algorithms (e.g., variational algorithms, Trotterized dynamics) where the overhead of full error correction is prohibitive.

The authors remain modest regarding the scope, noting that the framework currently relies on specific code properties (transversal gates) and that rigorous analysis of error propagation in clean-noisy gates remains an open question. They also highlight that the framework does not yet solve the problem of implementing non-Clifford gates fault-tolerantly, suggesting that non-Clifford operations might still need to be performed on noisy registers or via resource-intensive distillation.