🔬 applied physics

Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

This paper establishes critical system-level requirements for controller-decoder systems to successfully execute non-Clifford quantum circuits, specifically Shor's algorithm for factoring 21 using surface codes, demonstrating that near-term superconducting hardware with 0.1% error rates and 1,000 qubits can achieve fault-tolerant execution provided the controller-decoder closed-loop latency remains within tens of microseconds.

Original authors: Yaniv Kurman, Lior Ella, Nir Halay, Oded Wertheim, Yonatan Cohen

Published 2026-07-17

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CC BY 4.0

Original authors: Yaniv Kurman, Lior Ella, Nir Halay, Oded Wertheim, Yonatan Cohen

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine a world where computers don't just calculate numbers but manipulate the very fabric of reality, solving problems in seconds that would take today's supercomputers thousands of years. This is the promise of quantum computing. But there's a catch: these machines are incredibly fragile. Like a house of cards in a hurricane, the tiniest whisper of noise or a stray vibration can knock the whole thing over, ruining the calculation. To fix this, scientists use a safety net called "Quantum Error Correction" (QEC). Think of QEC as a team of vigilant guards watching over a fragile secret. They constantly check if the secret has been tampered with and fix any mistakes immediately. However, for this system to work, the guards need to be incredibly fast and smart. If they take too long to spot a mistake and shout a correction, the house of cards collapses before they can save it. The big question scientists are asking right now is: just how fast and powerful do these "guards" and their communication systems need to be to run the most complex quantum magic tricks, like breaking secret codes or simulating new medicines?

This paper dives deep into that question by simulating a specific, tricky quantum task: factoring the number 21 using a famous algorithm called Shor's algorithm. The authors, researchers from Quantum Machines Inc., act like architects designing the ultimate control room for a quantum computer. They break down the entire process, from the high-level math to the nitty-gritty of the physical chips, to figure out the exact rules the "controller-decoder system" (the brain and nervous system of the quantum computer) must follow to succeed.

Here is what they found: To run this complex quantum trick successfully, the system needs to be a speed demon. The time it takes for the system to spot an error and send a correction back to the quantum chip must be incredibly short—within just a few tens of microseconds. That's faster than a blink of an eye! The authors simulated this scenario using a model of a superconducting quantum chip (the kind used by companies like Google and IBM) with about 1,000 physical qubits (the tiny switches that make up the computer) and a physical error rate of 0.1%. Their simulations suggest that with these specs, the computer could successfully perform the calculation.

However, the paper also highlights a major bottleneck: the "magic state." To perform the most advanced quantum moves, the computer needs special ingredients called magic states. The authors found that if these ingredients aren't prepared with extreme care, they become the weak link, causing errors no matter how good the rest of the system is. They suggest that for the near future, we don't need millions of qubits; a chip with around 1,000 qubits and a very low error rate is enough, provided the controller-decoder system is fast enough to keep up.

The paper also rules out the idea that we can just wait until the end to fix errors. For these advanced circuits, the system must make decisions while the calculation is happening. If the system waits too long to send a correction, the quantum state gets messy, and the calculation fails. The authors show that the system needs to handle multiple correction tasks at the same time, like a traffic controller managing four different intersections simultaneously, ensuring that no single delay causes a crash.

In short, this paper doesn't just say "we need better computers." It gives a specific blueprint. It tells engineers that if they can build a control system that communicates in microseconds and manages about 1,000 qubits with a 0.1% error rate, they can successfully run the next big milestone in quantum computing. It's a roadmap for turning the fragile house of cards into a sturdy skyscraper, one fast correction at a time.

Technical Summary: Controller-Decoder System Requirements for Non-Clifford Surface Code Circuits

Problem Statement

Quantum Error Correction (QEC) is widely regarded as the primary pathway to achieving quantum advantage. While significant progress has been made in demonstrating fault-tolerant (FT) Clifford circuits and extending qubit lifetimes, a critical gap remains in executing non-Clifford circuits, which are essential for universal quantum computation.

The execution of non-Clifford circuits (such as Shor's algorithm) introduces a fundamental constraint absent in Clifford-only circuits: decoding-dependent feed-forward. Unlike Clifford operations where measurement outcomes can be tracked virtually via Pauli frames, non-Clifford gates (e.g., T-gates) often require physical corrections based on real-time decoding results. This necessitates a Controller-Decoder System (CDS) capable of:

Processing syndrome data in real-time.
Making decoding-dependent decisions (branching).
Executing feed-forward gates within a strict latency budget to prevent logical qubits from idling excessively, which would accumulate errors.

Prior to this work, there was a lack of comprehensive, end-to-end analysis specifying the concrete system-level requirements (latency, throughput, resource allocation) for a CDS to successfully execute a non-Clifford QEC circuit.

Methodology

The authors perform an end-to-end analysis based on a representative non-Clifford circuit: Shor's factorization algorithm for the number 21. The methodology proceeds through four distinct levels of abstraction:

Logical to Surface-Level Mapping:
- The logical circuit is converted into a surface-code compatible circuit using a native gate set (Clifford gates, lattice surgery, and magic-state preparation).
- The circuit is compiled into a surface-level implementation involving 18 surfaces (5 computational, 13 ancillary) arranged on a 2D grid with nearest-neighbor connectivity.
- The circuit includes 13 decoding tasks corresponding to non-Clifford operations, with parallel processing requirements of up to 4 simultaneous tasks.
Physical-Level Simulation:
- The surface-level circuit is compiled into a physical-level circuit using the stim simulator, extended to handle the specific compilation logic for surface codes.
- To address stim's limitation regarding non-Clifford gates, the authors simulate the circuit using S-gates (Clifford) in place of T-gates and |S⟩-state injections instead of |T⟩-state injections. The error contribution of the non-FT magic-state initialization is inferred separately and added to the total error budget.
- Simulations are run for physical error rates ( $P_{phys}$ ) of 0.1% and 0.3%, and code distances ( $d$ ) ranging from 3 to 9.
Error Budget Analysis:
- The total logical error is estimated by summing contributions from FT gates (which scale exponentially with $d$ ) and magic-state initializations (which are largely distance-independent for injection methods).
- The target logical error is set at 8.6% to maintain the statistical dominance of the correct factorization outcomes.
Decoding and Latency Modeling:
- The circuit is decomposed into 13 distinct decoding tasks.
- The authors model the CDS latency (time from the last measurement of a task to the execution of the dependent feed-forward gate).
- They calculate the additional logical error introduced by latency delays ( $P_{delay}$ ) as a function of the number of idle stabilizer rounds.

Key Results

1. Hardware Requirements for Successful Execution

Physical Error Rate: A physical error rate of 0.1% is required. At 0.3%, the circuit fails to meet the error threshold regardless of the code distance.
Code Distance: A code distance of $d=5$ is sufficient. Increasing $d$ beyond 5 yields diminishing returns because the error budget is dominated by non-FT magic-state initializations (injection) rather than FT gate errors.
Qubit Count: Approximately 1,000 physical qubits (specifically 1,015 for $d=5$ ) are sufficient to execute the circuit.
Run Time: A single shot of the circuit requires approximately 100–350 µs on superconducting hardware.

2. Controller-Decoder System (CDS) Latency

Latency Budget: The closed-loop latency (controller + decoder + communication) must remain within tens of microseconds.
Error Impact: For a circuit with $d=5$ and $P_{phys}=0.1\%$ , a delay of up to 50 µs adds less than 0.3% to the total logical error. The total delay budget for the circuit is approximately 400 µs.
Parallelism: The system must support parallel decoding. In the analyzed circuit, up to 4 decoding tasks must be processed simultaneously, with dependencies between tasks (shape and frame dependencies) requiring inter-decoder communication.

3. Resource and Throughput Estimates

Bandwidth: The data generation rate requires a channel bandwidth of approximately 1 Mbit/s per active qubit (assuming 1 µs stabilizer rounds).
Decoder Complexity: For low error rates (0.1%), decoding tasks are sparse, with an average of only a few tens of syndromes per task. This suggests that embedded decoders (e.g., FPGA-based) or pre-decoder stages are viable for near-term implementations.
Control Channels: While the total qubit count is ~1,000, only 55–65% of qubits are active simultaneously, allowing for multiplexed control strategies.

Key Contributions

End-to-End Breakdown: The paper provides the first detailed, step-by-step breakdown from a logical non-Clifford circuit to physical-level requirements, moving beyond high-level resource estimates.
Concrete Latency Targets: It establishes specific latency targets (tens of microseconds) for the CDS, demonstrating that near-term hardware performance is sufficient if the feedback loop is fast enough.
Decoding Architecture Insights: The authors argue for a shift from single-decoder architectures to multi-task decoding units that can handle parallel tasks with explicit dependency management (shape and frame updates).
Magic-State Dominance: The analysis highlights that for near-term circuits, the error budget is dominated by magic-state initialization rather than FT gate errors, suggesting that improving initialization fidelity (e.g., via cultivation) is more critical than simply increasing code distance.

Significance and Claims

The paper claims to set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits. By outlining specific requirements for the controller, communication channel, and decoding unit, the authors provide a foundational framework for advancing toward scalable fault-tolerant quantum computation.

The authors emphasize that their findings indicate that current or near-future hardware scales (0.1% error rates, ~1,000 qubits) are sufficient for successful execution, provided the CDS can meet the derived latency and throughput constraints. The work serves as a practical specification guide for building the control systems necessary to transition from Clifford-only demonstrations to universal, error-corrected quantum algorithms.