Running a six-qubit quantum circuit on a silicon spin qubit array

Technical Summary: Running a Six-Qubit Quantum Circuit on a Silicon Spin Qubit Array

Problem Statement
While semiconductor-based quantum computing offers a promising path toward scalability through industry-standard microchip integration, the field has historically struggled to move beyond first-principles demonstrations of the DiVincenzo criteria. Specifically for silicon-based quantum dots, despite the availability of devices containing more qubits, the validation of universal logic has been limited to three-qubit algorithms. A critical bottleneck for scaling these noisy intermediate-scale devices is the accumulation of errors when multiple units are operated collectively, leading to slowed processor operation and a limiting coherence budget. Previous works characterized single-qubit operations in larger arrays or demonstrated simultaneous tuning in six-qubit devices but had not yet executed entangling circuits involving all available qubits in a single processor.

Methodology
The authors utilized a linear array of six single-electron spin qubits defined electrostatically within a $^{28}$Si/SiGe heterostructure. The device operates at 200 mK to mitigate microwave-induced heating. The experimental workflow involved:

1. Initialization and Readout: The team employed an extended readout scheme to measure the "return probability" (overlap between initial and final states). This required overcoming the inherent limitations of Parity-mode Pauli Spin Blockade (PSB), which cannot distinguish between $|\uparrow\uparrow\rangle$ and $|\downarrow\downarrow\rangle$. They implemented a protocol using two-qubit logic (CNOT gates compiled from native ZZ interactions) to isolate the $|\downarrow\rangle^{\otimes N}$ state. Qubits 3 and 4 were read out via Quantum Non-Demolition (QND) measurements, while qubits 1, 2, 5, and 6 utilized PSB. State preparation involved measurement and post-selection.
2. Circuit Implementation: The researchers executed a digital quantum circuit inspired by a protocol for investigating dynamical quantum phase transitions (DQPTs) in Ising-like systems. The circuit simulates a quantum quench where an initial ground state $|\downarrow\rangle^{\otimes N}$ evolves under an interaction Hamiltonian involving nearest-neighbor XX couplings and boundary terms.
3. Scalability Testing: The circuit was run across all permutations of $N \in \{3, 4, 5, 6\}$ neighboring qubits. The time evolution was parameterized by an angle $\theta$, controlled by the duration of microwave bursts.
4. Characterization: The team measured the Loschmidt echo amplitude (return probability) and magnetization. They also performed full Quantum State Tomography (QST) on subsets of three and four qubits to assess state fidelity and entanglement. To understand performance limits, they measured $T_2^*$ (dephasing times) under various exchange coupling conditions ($J_{on}$ and $J_{off}$) and compared experimental data against numerical simulations incorporating quasi-static phase noise.

Key Results

• Six-Qubit Execution: The study successfully implemented a quantum circuit utilizing all six qubits in the array, marking the largest quantum circuit executed on semiconductor technology to date.
• Programmability: The processor demonstrated successful programmable multi-qubit operation across all permutations of three, four, five, and six neighboring qubits.
• Dynamics and Scaling: The experimental return probability exhibited the expected periodic dynamics ($\theta = \pi$) and critical behavior ($\theta_c = \pi/2$) predicted by the theoretical model. As the number of qubits ($N$) increased, the Loschmidt echo showed broader and deeper minima, consistent with the analytical scaling $L(\theta) = |\cos(\theta/2)^{N+1} + i^{N+1}\sin(\theta/2)^{N+1}|^2$.
• Error Accumulation: Despite high-fidelity individual units, errors accumulated rapidly as the system size increased. The return probability at $\theta=0$ dropped with increasing $N$, and visibility decreased significantly for larger $N$.
• Dephasing and Idling: Analysis revealed that idling times for specific qubits often exceeded their $T_2^*$ coherence times, particularly for edge qubits (1, 2, and 5) in larger circuits. Numerical simulations incorporating quasi-static dephasing noise qualitatively reproduced the experimental trends, confirming that dephasing during idle periods is a primary performance limiter.
• State Fidelity: QST results for three-qubit states (including GHZ states and the final quench state) showed fidelities comparable to state-of-the-art semiconductor platforms. The authors noted an improvement in phase stability compared to previous work on the same device, attributed to operation at 200 mK which reduced microwave crosstalk.

Significance and Claims
The paper claims to demonstrate the first execution of a realistic, multi-qubit quantum circuit on a semiconductor spin-qubit device involving a register of up to six qubits. The work serves as a holistic benchmark of the processor's capabilities, moving beyond isolated gate characterization to assess collective performance under a realistic workload.

The authors conclude that while the platform has achieved significant milestones in control and readout, the current generation of these devices is fundamentally limited by dephasing (specifically during idling) and state preparation and measurement (SPAM) errors. The results highlight the necessity for:

1. Minimizing idling times through simultaneous (parallel) operations.
2. Boosting dephasing times ($T_2^*$).
3. Consistently improving SPAM fidelities.

The study does not claim to have achieved fault tolerance or logical error correction but rather establishes a baseline for the collective behavior of silicon spin qubits, identifying specific physical bottlenecks that must be addressed to scale toward more complex quantum algorithms.