🔬 applied physics

A CMOS+X Spiking Neuron With On-Chip Machine Learning

This paper presents a CMOS+X spiking neuron design combining an NMOS transistor and a magnetic tunnel junction (MTJ) that intrinsically replicates biological neuron behaviors and enables on-chip analog machine learning, successfully demonstrating training and inference on an XOR task without additional control circuitry.

Original authors: Steven Louis, Matthew Blake Abramson, Hannah Bradley, Cody Trevillian, Gene David Nelson, Andrei Slavin, Artem Litvinenko, Jason Gorski, Ilya N. Krivorotov, Darrin Hanna, Vasyl Tyberkevych

Published 2026-08-12

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Steven Louis, Matthew Blake Abramson, Hannah Bradley, Cody Trevillian, Gene David Nelson, Andrei Slavin, Artem Litvinenko, Jason Gorski, Ilya N. Krivorotov, Darrin Hanna, Vasyl Tyberkevych

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine trying to build a super-smart computer that fits in your pocket and runs on a single battery, capable of learning new tricks in real-time. Today's computers are like massive, energy-hungry libraries where every single book must be read and re-read to find a single fact. They are fast, but they burn a lot of power and take up a lot of space. Scientists are looking for a different way: a computer that works more like a human brain. Instead of constantly reading books, a brain waits for a signal—a "spike"—and only does work when something interesting happens. This is called a "spiking neural network." It's like a city where lights only turn on when someone walks by, saving electricity. But building a brain-like chip out of the standard silicon we use for phones and laptops is tricky. The standard parts are great at math, but they aren't very good at mimicking the messy, biological way neurons fire. So, researchers are asking: can we mix our standard computer parts with some new, exotic materials to create a chip that thinks like a brain?

In this paper, a team of researchers explores a clever solution called "CMOS+X." Think of "CMOS" as the standard, reliable Lego bricks we use to build all our current electronics. The "X" is a special, new piece they want to snap onto those bricks to give them brain-like powers. In this specific study, the "X" is a tiny magnetic switch called a Magnetic Tunnel Junction (MTJ). These are the same kinds of switches used in some modern memory chips, but the researchers are using them in a new way. They pair this magnetic switch with a single standard transistor (a tiny electronic valve) to create a brand-new kind of artificial neuron. The big question they are asking is: Can this simple pair of parts, working together, actually act like a biological neuron? Can it wait for a signal, decide if it's strong enough, and then "fire" a spike? And even more importantly, can a whole network of these things learn a difficult puzzle just by watching its own mistakes?

The researchers built a virtual version of this system using a popular computer program called LTspice, which is like a simulator for electronic circuits. They didn't build a physical chip in a lab for this specific test; instead, they created a highly detailed digital model to see if the physics would work out. Their main finding is that this "NMOS+MTJ" pair does indeed behave like a biological neuron. When they sent a voltage signal into it, the magnetic part inside would spin and shift, creating a sharp "spike" in the output voltage, just like a real neuron firing. This happened without any complex extra wiring or digital computers telling it what to do; the behavior came naturally from the physics of the magnetic materials.

The paper shows that these artificial neurons can do all the cool things real neurons do. They have a "threshold," meaning they ignore weak whispers and only shout (spike) when the signal is loud enough. They have "latency," where a stronger signal makes them fire faster, and a weaker signal makes them wait a bit longer. They even have a "refractory period," a short rest time after firing where they can't fire again immediately, just like a real brain cell needs a moment to recharge. They can also "integrate" signals, adding up several small nudges over time until they finally reach the point of firing.

The team then connected these neurons together to form a small network, linking them with "synapses" (which they modeled as adjustable amplifiers). They taught this network to solve the XOR problem, a classic logic puzzle that is too tricky for simple, single-layer computers but easy for a brain. The network learned by adjusting the strength of the connections between neurons based on a rule called "gradient descent." In the simulation, the network would try to solve the puzzle, see how wrong its timing was, and then tweak the connections to get closer to the right answer. After about 16 rounds of trying and correcting, the network successfully learned the pattern. The output spikes lined up perfectly with the target times, proving that the system could learn a complex, non-linear task entirely within the analog circuit simulation.

The authors are careful to note that this is a proof-of-concept simulation. They haven't built a physical chip that does this yet, and they haven't tested how it would handle real-world imperfections like heat or manufacturing errors. However, the simulation suggests that if we can build these circuits using standard manufacturing processes (since the magnetic parts are already used in memory chips), we could create a new kind of computer chip. This chip would be able to learn and process information right where the data is, using very little energy, which could be a game-changer for smart devices that need to run on batteries for a long time. The study opens the door to a future where our electronics don't just calculate numbers, but actually "think" in the same rhythmic, spike-driven way our brains do.

Technical Summary: A CMOS+X Spiking Neuron with On-Chip Machine Learning

Problem Statement
Modern edge-computing platforms face increasing demands for real-time intelligence under strict constraints on energy, latency, and silicon area. Conventional deep-learning architectures, reliant on dense matrix operations and high-precision arithmetic, are often computationally expensive and ill-suited for battery-powered or thermally limited devices. While Spiking Neural Networks (SNNs) offer an energy-efficient alternative through sparse, event-driven computation, their hardware implementation faces significant challenges. Digital SNNs suffer from memory bottlenecks and clock-synchronous overhead, while analog implementations require novel device physics to realize compact neurons and tunable synapses without relying on digital control or separating memory from computation. There is a need for a manufacturable, CMOS-compatible hardware framework that can natively support both spiking behavior and on-chip learning.

Methodology
This work proposes and simulates a "CMOS+X" framework, where "X" represents a spintronic Magnetic Tunnel Junction (MTJ) integrated with standard CMOS technology. The core of the methodology involves:

Device Architecture: The authors design a single artificial neuron consisting of an NMOS transistor connected in series with an MTJ (an NMOS+MTJ unit). This structure mirrors the standard 1T-1MTJ cell used in MRAM but is repurposed for dynamic operation. The MTJ features a reference layer, an analyzer layer, and a free layer. The resistance of the MTJ depends on the angle between the free layer's magnetization and the analyzer layer.
Operating Principle: The neuron operates via Spin-Transfer Torque (STT). An input voltage ( $V_{in}$ ) controls the gate of the NMOS transistor, regulating the current ( $I_{D}$ ) flowing through the series circuit. This current exerts a torque on the free layer's magnetization, causing it to precess. When the magnetization angle exceeds a specific threshold, the MTJ resistance undergoes a sharp, temporary change, generating a voltage spike at the output ( $V_{out}$ ).
Simulation Environment: The system is modeled entirely within the industry-standard circuit simulator LTspice. The MTJ model incorporates magnetization dynamics (based on the Landau-Lifshitz-Gilbert equation with STT terms), while the NMOS uses a default model. The study assumes isothermal conditions and does not include process variations or thermal fluctuations.
Network and Learning: The authors interconnect these neurons using analog synapses modeled as tunable voltage amplifiers. They construct a two-layer feedforward network (input and output layers) plus external encoding neurons to solve the non-linear XOR classification task. Learning is achieved through a supervised, gradient-descent rule adapted for the analog domain. The learning mechanism relies on time-encoded spike signals, where the firing time of the output neuron is adjusted to match a target "goal" spike time. The weight update rule is derived from the derivative of a loss function (the squared difference between actual and desired firing times) with respect to synaptic weights.

Key Contributions

Novel Neuron Design: The paper demonstrates that an NMOS+MTJ pair, a structure nearly identical to standard MRAM cells, naturally reproduces essential biological neuron behaviors—including threshold activation, spike generation, latency, refractory periods, synaptic integration, and inhibition—without additional control circuitry. These behaviors emerge intrinsically from the coupled device physics of the MTJ and transistor.
Analog On-Chip Learning: The work presents a proof-of-concept for a fully analog, on-chip learning system. It demonstrates that a network of these physical neurons can perform supervised gradient-descent learning directly within the analog domain, using spike-timing-dependent weight updates.
XOR Classification: The authors successfully simulate a two-layer spiking neural network that learns the non-linear XOR task. The network adjusts its synaptic weights over training epochs until the output spike timing aligns with the target logic values.

Results

Single-Neuron Dynamics: LTspice simulations confirmed that the NMOS+MTJ neuron exhibits "all-or-nothing" spiking behavior. Inputs below a threshold voltage ( $V_{th} \approx 3.4$ V) fail to trigger a spike, while inputs above the threshold generate a consistent spike shape regardless of amplitude. The system also demonstrated response latency (delay decreases with stronger inputs), refractory periods (absolute and relative), and frequency modulation.
Signal Propagation: A chain of three neurons connected by tunable synapses successfully propagated spikes. The simulations showed that synaptic weight (amplifier gain) directly influences response latency, establishing a trade-off between timing tunability and sensitivity.
Learning Performance: The network trained on the XOR task converged after approximately 16 epochs.
- Weight Convergence: Synaptic weights stabilized to specific values (e.g., $w_{o1i1} \approx 3.63$ , $w_{o1i2} \approx 6.19$ ).
- Error Reduction: The loss function dropped sharply after epoch 16, approaching zero.
- Accuracy: By epoch 22, the maximum absolute timing error across all four XOR input conditions was reduced to 0.102 ns. The output spikes closely matched the target "goal" spikes for all input combinations.
- Efficiency: The entire training process for the XOR task was simulated in approximately 15 seconds on a conventional laptop, with a total simulated training time of about 1 $\mu$ s.

Significance and Claims
The paper claims to provide a proof-of-concept for a CMOS+X neuromorphic architecture that integrates training and inference within a single analog platform. The authors emphasize that this is the first circuit-level simulation where physically generated neuron dynamics (derived from MTJ magnetization) participate directly in supervised learning within a spiking neural network.

The significance lies in demonstrating that:

Standard semiconductor manufacturing flows (specifically those supporting MRAM) could potentially realize these neuromorphic circuits.
Complex, non-linear learning tasks can be modeled using only analog circuitry and time-encoded signals, eliminating the need for digital backpropagation or surrogate gradients in the simulation.
The intrinsic physics of spintronic devices can serve as the computational substrate for both neuron dynamics and learning, bridging the gap between nanoscale spintronics and CMOS-compatible analog electronics.

The authors remain modest regarding the current scope, noting that the work is a simulation-based proof-of-concept without experimental validation, process variation analysis, or a full power/energy evaluation of the idealized synapse models. They identify experimental validation, transistor-level implementation of synapses, and robustness testing as necessary future steps.

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