⚛️ quantum physics

Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search with Uncertainty Calibrated Surrogates

This paper presents a graph-based Bayesian optimization framework utilizing a GNN surrogate with Monte Carlo dropout for uncertainty calibration to automatically discover efficient and robust variational quantum circuits for cybersecurity classification tasks.

Original authors: Prashant Kumar Choudhary, Nouhaila Innan, Muhammad Shafique, Rajeev Singh

Published 2026-07-14

📖 6 min read🧠 Deep dive

CC BY 4.0

Original authors: Prashant Kumar Choudhary, Nouhaila Innan, Muhammad Shafique, Rajeev Singh

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to build the perfect quantum computer circuit to solve a tricky puzzle, like spotting a cyber-attack in a massive stream of network traffic. The problem is that there are so many ways to arrange the tiny quantum "gates" (the building blocks of the circuit) that trying every single combination is like trying to read every book in a library the size of the universe just to find one good story. It's impossible.

This paper introduces a smart, automated detective called Graph-Based Bayesian Optimization to find the best circuit design without checking every single possibility. Here is how it works, using some fun comparisons.

The Problem: The "Flat" vs. "3D" Map

Usually, when computers try to guess which circuit design is good, they look at a simple list of numbers, like "total number of gates" or "how deep the circuit is." The authors argue that this is like judging two different cities just by counting how many buildings they have. Two cities might have the same number of buildings, but one could be a messy sprawl and the other a perfectly organized grid. The simple list misses the shape and connections of the city.

The paper explicitly argues against using these simple, flat lists of numbers (which they call "fixed-vector surrogates" or MLPs) because they collapse unique circuit shapes into identical-looking numbers. Instead, the authors propose treating every circuit as a graph—a map where the gates are dots and the connections between them are lines. This preserves the unique "topology" or shape of the circuit, just like a real map preserves the layout of streets.

The Solution: The Uncertainty-Aware Architect

The authors built a system that acts like a super-smart architect who learns as they go.

The Graph Neural Network (GNN): This is the architect's brain. It looks at the circuit's graph map. The authors specifically used a type of brain called a Graph Isomorphism Network (GIN) because it is really good at telling the difference between two graphs that look similar but are actually different.
The "Gut Feeling" (Uncertainty): The architect doesn't just guess; they also know how unsure they are. The system uses a trick called Monte Carlo dropout, which is like asking the architect to make the same prediction 30 times with slightly different "moods" to see how much their answers vary. If the answers vary a lot, the system knows, "I'm not sure about this one, let's explore it!" If they are all the same, the system knows, "I'm confident."
The Cost of Reality: The system doesn't just look for the most accurate circuit; it also looks for one that won't break on real hardware. It adds a "penalty" for circuits that are too deep, have too many two-qubit gates (which are prone to errors), or would require too many extra "SWAP" operations to fit on a real quantum chip.

The Experiment: A Cybersecurity Test Drive

To test this, the researchers used a dataset called NF-ToN-IoT-V2, which contains 10,000 samples of network traffic (some normal, some attacks). They treated this like a training ground.

They set up a Bayesian Optimization loop: The system suggests a circuit, tests it, learns from the result, and suggests a better one.
They tested circuits with 8, 10, and 12 qubits (the quantum bits).
They compared their graph-based method against:
- Random Search: Picking designs by throwing darts.
- Greedy GNN: Just picking the one that looks best right now without thinking ahead.
- MLP Surrogate: The "flat list" method they argued against.

The Results: What the Simulations Showed

The paper ran these tests on a supercomputer (specifically the PARAM Shivay at IIT BHU) using simulations. They did not run these on actual physical quantum hardware, but they simulated the noise you would find on real machines.

Better Accuracy: The graph-based method (BO+VQC+GNN) consistently found circuits that were more accurate at classifying the network traffic than the other methods. For example, with 12 qubits, it achieved a test accuracy of 94.25%, beating the next best method (BO+VQC+MLP) which got 92.95%.
Smarter Circuits: The circuits found by the graph method were "leaner." They achieved high accuracy with fewer gates and less depth, meaning they are more efficient.
Noise Resilience: The authors tested how the circuits held up under different types of "noise" (errors that happen in real quantum computers).
- Interestingly, the circuits actually performed slightly better (up to +3.45% in accuracy) under amplitude damping and thermal relaxation noise compared to a perfect, noise-free simulation. The authors suggest this is because the noise acted like a gentle regularizer, smoothing out the decision boundaries.
- However, depolarizing noise (a type of random error) was the worst, dropping accuracy by about 3.24%.
- The system showed that circuits designed with this method stay robust even when the "coherence times" (how long the qubits stay stable, measured in microseconds) vary.

What the Paper Rules Out and Limits

The authors are careful to state what their method is not.

They explicitly rule out the idea that simple lists of numbers (like just counting gates) are enough to design good circuits. Their data suggests these flat methods miss critical structural details.
They admit that their results are based on simulations. While they simulated realistic noise (like amplitude damping, phase damping, and readout bit-flip errors with a probability of 0.02), they did not run these specific circuits on a physical quantum device yet. They acknowledge that real hardware might behave differently.
They note that while their method is efficient, the "wall-clock time" (real-world time) is mostly dominated by the time it takes to train the quantum model, not by the graph analysis itself.

The Bottom Line

This paper suggests that if you want to automatically design quantum circuits, you should stop treating them like a bag of numbers and start treating them like a map. By using a graph-based brain that knows how to be unsure when it's guessing, and by penalizing designs that are too expensive or fragile, you can find circuits that are both accurate and efficient. The authors found that this approach works well in their simulations, producing circuits that are robust against common types of noise and outperform older search methods, but they remind us that the final test on real hardware is still a job for the future.

Technical Summary: Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search

1. Problem Statement

The design of Variational Quantum Circuits (VQCs) is a critical bottleneck for practical Quantum Machine Learning (QML), particularly for tasks involving complex, real-world data. The performance of a VQC relies heavily on its architectural design—the arrangement, type, and connectivity of quantum gates—rather than just its continuous parameters. However, searching this design space is a high-dimensional, non-convex optimization problem. As the number of qubits and circuit depth increase, the combinatorial search space renders brute-force enumeration intractable.

Existing automated quantum architecture search methods face several specific challenges:

Representation Limitations: Many approaches rely on fixed-size vector surrogates (e.g., counting total gates or depth), which collapse structurally distinct (non-isomorphic) circuits into similar feature vectors, failing to capture topological nuances.
Uncertainty Miscalibration: Bayesian Optimization (BO) requires surrogates that provide calibrated epistemic uncertainty to balance exploration and exploitation. Standard methods often lack this calibration.
Hardware Insensitivity: Search processes often ignore routing overheads (extra SWAP/CNOT gates) and decoherence effects (relaxation and dephasing) that occur during transpilation to real hardware, leading to designs that perform well in simulation but fail on devices.
Search Bloat: Algorithms often drift toward deep, two-qubit-heavy layouts that are infeasible on Noisy Intermediate-Scale Quantum (NISQ) devices.

2. Methodology

The authors propose a unified, end-to-end framework that integrates Graph-Based Bayesian Optimization with a Graph Neural Network (GNN) surrogate to automate the discovery of robust, hardware-efficient VQCs.

2.1 Graph Representation

Instead of using scalar feature vectors, circuits are encoded as Directed Acyclic Graphs (DAGs).

Nodes: Represent gate operations (e.g., $R_X, R_Z, CZ, CX$ ) with features including one-hot gate type, normalized temporal position, and qubit incidence.
Edges: Capture temporal adjacency and shared-qubit connectivity.
Surrogate Model: A lightweight Graph Isomorphism Network (GIN) is employed as the surrogate. GINs are chosen for their strong graph discrimination power (Weisfeiler-Lehman test level). To estimate epistemic uncertainty, the GNN utilizes Monte Carlo (MC) dropout during inference, generating a distribution of predictions rather than a single point estimate.

2.2 Bayesian Optimization Loop

The search process follows a standard BO loop but with hardware-aware modifications:

Candidate Generation: New circuits are generated via local mutations (gate insertion, replacement, or removal) applied to a parent pool of top-performing circuits.
Surrogate Scoring: The GIN surrogate predicts the validation performance ( $\hat{\mu}$ ) and uncertainty ( $\hat{\sigma}$ ) for candidate graphs.
Acquisition Function: The authors introduce a cost- and noise-aware Expected Improvement (EI) acquisition function. The standard EI is tempered by an exponential cost term:
$ACQ = EI(\hat{\mu}, \hat{\sigma}) \cdot \exp(-\alpha \cdot C_{total})$
Where $C_{total}$ aggregates normalized structural costs (depth, total gates, two-qubit gate counts, CZ counts) and a decoherence proxy derived from gate times relative to $T_1$ and $T_2$ relaxation times. This penalizes deep, highly entangled circuits that are prone to decoherence and mapping overheads.
Evaluation: The top- $k$ candidates selected by the acquisition function are evaluated using a hybrid quantum-classical variational classifier on the NF-ToN-IoT-V2 cybersecurity dataset.
Update: The surrogate is retrained on the new data points.

2.3 Noise Modeling

To ensure robustness, the framework incorporates realistic noise models during evaluation, including:

Amplitude Damping (AD) and Phase Damping (PD).
Thermal Relaxation (Generalized Amplitude Damping + PD).
Depolarizing noise.
Readout bit-flip errors.
Sweeps over $T_1$ and $T_2$ coherence times to map performance landscapes.

3. Key Contributions

The paper claims the following specific contributions:

Structure-Aware Surrogate: The use of a GIN surrogate with MC dropout to predict VQC performance and calibrated uncertainty, preserving topological information lost in scalar feature representations.
Cost and Noise-Aware Acquisition: A tempered EI objective that integrates normalized complexity metrics and a decoherence-aware penalty, biasing the search toward hardware-feasible circuits.
Hardware-Realistic Optimization: The integration of compilation-induced costs (routing, SWAPs) and decoherence models directly into the BO loop to narrow the simulator-to-device gap.
Comprehensive Noise Study: Extensive evaluation of circuit robustness across various noise channels and coherence time sweeps ( $T_1 \times T_2$ ).
Fair Evaluation and Reproducibility: Experiments conducted on a balanced subset of the NF-ToN-IoT-V2 dataset with leakage-free preprocessing, comparing against MLP-based BO, greedy GNN selection, and random search. All artifacts (code, circuits, metrics) are intended for public release.

4. Experimental Results

The framework was evaluated on the NF-ToN-IoT-V2 dataset (network traffic classification) across varying qubit counts (5, 8, 10, and 12).

Performance: The BO+VQC+GNN approach consistently outperformed baselines (BO+VQC+MLP, Greedy GNN, Random Search) in terms of validation and test accuracy. Notably, at 12 qubits, the GNN-based method achieved 94.25% test accuracy, significantly outperforming the MLP-based surrogate (92.95%) and random search (83.55%).
Convergence: The GNN-guided optimizer demonstrated faster convergence and better sample efficiency. It achieved early and stable convergence, whereas the MLP baseline showed slower improvement and occasional stalls, particularly with higher mutation budgets.
Surrogate Fidelity: The ranking fidelity (measured by Kendall's $\tau$ ) of the GNN surrogate improved steadily with iterations, indicating that the graph-based representation effectively learned to rank candidates correctly as more data accumulated.
Pareto Efficiency: The method identified circuits on the Pareto frontier that achieved high accuracy with lower complexity (fewer gates and shallower depth) compared to baselines. The results highlighted diminishing returns for overly deep circuits, validating the cost-tempering mechanism.
Noise Robustness: The learned circuits exhibited strong robustness. Interestingly, under amplitude damping and thermal relaxation, the test accuracy slightly improved compared to the noise-free baseline (likely due to a regularizing effect), while depolarizing noise caused the most significant degradation. The circuits maintained performance across a wide range of $T_1$ and $T_2$ values.
Efficiency: Wall-clock time analysis showed that the GNN surrogate added negligible overhead compared to the VQC evaluation time, making the graph-based approach scalable.

5. Significance and Claims

The paper positions this work as a practical step toward scalable QML on near-term architectures. The authors claim that by automating circuit discovery with a structure-aware, uncertainty-calibrated surrogate and physics-informed acquisition, they can generate circuits that are simultaneously accurate, efficient, and robust.

Key takeaways emphasized by the authors include:

Overcoming Representation Limits: Graph encodings are superior to scalar features for distinguishing circuit function and topology.
Bridging the Gap: Integrating transpiler costs and decoherence models into the search loop prevents the discovery of "simulation-only" circuits that fail on real hardware.
Scalability: The framework scales smoothly with qubit count without exploding in computational cost, offering a reproducible route to automated quantum circuit design.

The authors acknowledge limitations, noting that the primary evaluation relies on simulators (which may overestimate on-device performance) and that complexity is treated via a light penalty rather than a full multi-objective optimization. Future work is suggested to include multi-fidelity BO, richer operator sets, and direct optimization on quantum hardware.