💻 computer science

SRAM-Based Compute-in-Memory Accelerator for Linear-decay Spiking Neural Networks

This paper proposes an SRAM-based Compute-in-Memory accelerator that co-optimizes a linear-decay neuron algorithm with an in-memory parallel update scheme to eliminate the state-update bottleneck in Spiking Neural Networks, achieving significant energy efficiency and latency improvements with negligible accuracy loss.

Original authors: Hongyang Shang, Shuai Dong, Yahan Yang, Junyi Yang, Peng Zhou, Arindam Basu

Published 2026-03-17

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CC BY 4.0

Original authors: Hongyang Shang, Shuai Dong, Yahan Yang, Junyi Yang, Peng Zhou, Arindam Basu

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are running a massive, high-speed factory that processes information. This factory is designed to mimic the human brain, specifically a type of "Spiking Neural Network" (SNN). In this brain-like factory, information doesn't flow constantly like a river; instead, it travels in tiny, discrete bursts called "spikes," much like a drummer hitting a snare drum only when necessary. This makes the factory incredibly energy-efficient.

However, this factory has a major traffic jam.

The Problem: The "Ticking Clock" Bottleneck

In a traditional brain-chip factory, every time a neuron (a worker) receives a signal, it has to do two things:

Add up the new signals (Synaptic operation).
Wait and decay (Membrane update): The worker's internal energy naturally leaks away over time, like a balloon slowly deflating.

The factory is great at step 1. It can add up signals for thousands of workers simultaneously (parallel processing). But step 2 is a disaster. The old design forces the factory to visit every single worker one by one to check their energy level and calculate how much it has leaked. If you have a million workers, the manager has to walk down a million aisles, one by one, to update them. This "serial" process is slow and burns a lot of energy, creating a bottleneck that slows down the whole factory.

The Solution: A New Factory Design

The researchers in this paper proposed a clever two-part fix to unblock the traffic jam. They call it an SRAM-based Compute-in-Memory (CIM) accelerator with Linear Decay.

1. The Algorithm Trick: "The Flat Line" vs. "The Curve"

The Old Way: In nature, energy leakage is exponential. Think of a hot cup of coffee cooling down. It cools fast at first, then slower and slower. To calculate this on a computer, you need complex math (multiplication), which is expensive and slow.

The New Way: The researchers said, "Let's simplify." Instead of a curved cooling line, let's pretend the energy leaks at a constant, straight-line rate.

Analogy: Imagine a leaky bucket. Instead of calculating exactly how the water level drops based on a complex curve, we just say, "Every second, exactly 1 cup of water falls out."
The Benefit: This turns a complex math problem (multiplication) into a simple one (subtraction). It's like swapping a supercomputer for a simple calculator. The result is almost identical (only about 1% less accurate), but it's lightning fast.

2. The Hardware Trick: "The Self-Updating Wall"

The Old Way: The factory manager had to walk to every worker, read their status, do the math, and write it back. This took time and energy.

The New Way: The researchers built the workers' desks (memory) right next to the math machines.

Analogy: Imagine a wall of lockers. In the old design, you had to open every locker, take out a piece of paper, walk to a desk to do math, and put it back. In the new design, the lockers themselves have little calculators built into them. When the door opens, the locker automatically subtracts the "leakage" value right there, without anyone leaving their seat.
The Benefit: Instead of walking down the aisle one by one, the whole wall updates all at once in just a few seconds. This is called "in-memory parallel update."

The Results: A Supercharged Factory

By combining these two tricks, the researchers achieved something amazing:

Speed: They updated the entire factory's state in a fraction of the time it used to take.
Energy: Because they stopped doing complex math and stopped walking the aisles, they saved a massive amount of electricity.
Efficiency: Their new design is 16 to 69 times more energy-efficient than previous top-tier designs.

The Big Picture

Think of this paper as the invention of a "smart, self-updating conveyor belt" for brain-like computers. Before, we were great at moving boxes (processing data) but terrible at checking the inventory (updating neuron states). Now, the inventory checks happen automatically as the boxes move, making the whole system faster, cheaper to run, and ready for real-world, battery-powered applications like smart sensors and robots.

In short: They stopped the factory from walking down the aisles one by one and taught the shelves to update themselves instantly, turning a slow, energy-hungry process into a sleek, high-speed operation.

1. Problem Statement

Spiking Neural Networks (SNNs) offer energy-efficient, event-driven computation but face a critical bottleneck in hardware implementation: the state update latency.

The Mismatch: While Compute-in-Memory (CIM) architectures can parallelize synaptic operations (Weight $\times$ Input) with $O(1)$ complexity, the subsequent neuron state update (membrane potential decay and accumulation) typically requires sequential access to all $N$ neurons.
The Bottleneck: This serial update process results in $O(N)$ latency and high energy consumption for memory access, negating the benefits of parallel synaptic computation.
Hardware Cost: Conventional Leaky Integrate-and-Fire (LIF) neurons use exponential decay, which requires hardware multipliers or lookup tables to implement, increasing area and power costs.

2. Methodology

The authors propose a co-optimized algorithm-hardware solution featuring an SRAM-based CIM architecture with a Linear Decay Leaky Integrate-and-Fire (LD-LIF) neuron model.

A. Algorithmic Innovation: Linear Decay Approximation

Concept: The paper replaces the standard exponential membrane decay ( $V_{mem}(t) = V_0 e^{-t/\tau}$ ) with a linear decay approximation.
Mechanism: The update rule is simplified to:
$V_{mem}[t+1] = V_{mem}[t] - \beta + (W \cdot Input)$
Where $\beta$ is a fixed (or learnable) decrement representing leakage per timestep.
Benefit: This converts complex multiplications required for exponential decay into simple additions/subtractions, eliminating the need for multipliers and lookup tables.
Learnability: A learnable decay parameter $\beta$ is introduced for each layer during training to preserve accuracy, allowing the network to adapt the linear approximation to different temporal dynamics.

B. Hardware Architecture: SRAM-based In-Memory Parallel Update

The hardware design integrates the decay and update operations directly within the SRAM array to enable parallel processing.

Macro Structure: The accelerator consists of three main modules:
1. MAC Module: 32 SRAM blocks (256 rows $\times$ 4 units) performing 4-bit weight multiplication and accumulation via an adder tree.
2. Scaler Module: Aligns the MAC output with the 10-bit membrane potential (VMEM) resolution.
3. LD-LIF Module: Contains 32 VMEM submodules, each handling a 10-bit membrane potential.
Cell Design (VMEM Cell):
- Utilizes two 8T SRAM blocks (VMEM A and VMEM B) operating in a ping-pong fashion.
- Includes a Processing Element (PE) with a Full Adder (FA) and a 3-to-1 Multiplexer (MUX).
- Operation Cycle (3 Clock Cycles):
  1. Read & Add: Read $V_{init}$ from VMEM A, add MAC result, write intermediate $V_{mid}$ to VMEM B.
  2. Subtract Decay/Threshold: Read $V_{mid}$ from VMEM B, subtract $(\text{Decay} + \text{Threshold})$ , write $V'_{mid}$ back to VMEM A.
  3. Spiking Decision: Based on the sign bit of $V'_{mid}$ (indicating if the threshold was crossed), either reset to 0 (spike) or add the threshold back (no spike) and write $V_{final}$ to VMEM B.
Key Optimization: By subtracting the threshold alongside the decay value and using the sign bit for comparison, the design eliminates the need for a dedicated comparator circuit, reducing area and power.

3. Key Contributions

Algorithm-Hardware Co-Design: Successfully replaced exponential decay with a linear approximation that reduces computational complexity from multiplication to addition with negligible accuracy loss (~1%).
In-Memory Parallel State Update: Developed a novel SRAM-based CIM macro that performs membrane potential updates in-place and in parallel, removing the $O(N)$ serial latency bottleneck.
Comparator-Free Logic: Engineered a cell architecture that leverages arithmetic sign bits for spike detection, removing the overhead of comparison circuits.
SRAM Selection: Justified the use of SRAM over other CIM candidates (RRAM, PCM, MRAM) due to its superior read/write speed, stability, and CMOS compatibility for frequent state updates.

4. Results

The proposed method was evaluated on benchmark datasets (N-MNIST, SHD, DVS Gesture) using TSMC 65nm process simulations.

Accuracy:
- The LD-LIF model achieved accuracy comparable to the baseline vanilla LIF (v-LIF), with only 0.38% to 1.11% reduction in accuracy across different networks.
- Quantization (3-bit to 4-bit) showed similar performance degradation for both LD-LIF and v-LIF, confirming robustness.
Latency:
- The proposed architecture updates 32 membrane potentials in 3 clock cycles (total latency ~21 ns).
- This is approximately 30x faster than a conventional serial digital architecture operating at 200 MHz.
Energy Efficiency:
- SOP Energy: Achieved 0.09 pJ/SOP (Synaptic Operation).
- Improvement: Reduced SOP energy consumption by 1.1 $\times$ to 16.7 $\times$ compared to state-of-the-art works.
- TOPS/W: Achieved 20.7 TOPS/W, representing a 15.9 $\times$ to 69 $\times$ improvement in energy efficiency over existing digital and mixed-signal SNN accelerators.

5. Significance

This work demonstrates that optimizing the state-update dynamics is just as critical as accelerating synaptic computations for scalable neuromorphic processing. By shifting from exponential to linear decay and moving state updates into the memory array, the authors have created a pathway for real-time, low-power, and high-throughput SNN inference. This approach addresses the primary bottleneck in large-scale SNN deployment, making SRAM-based CIM a viable candidate for next-generation neuromorphic hardware.