🤖 machine learning

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

TimingLLM is a two-stage retrieval-augmented framework that predicts post-synthesis timing metrics (WNS and TNS) directly from Verilog by combining a fine-tuned LLM oracle that extracts structural-timing cues with an LLM-based regressor enhanced by k-nearest neighbor retrieval.

Original authors: Armin Abdollahi, Negin Ashrafi, Mehdi Kamal, Massoud Pedram

Published 2026-04-28

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CC BY 4.0

Original authors: Armin Abdollahi, Negin Ashrafi, Mehdi Kamal, Massoud Pedram

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are an architect designing a massive, complex skyscraper. In the world of computer chip design (Verilog), there is a huge problem: you don't know if your building will actually stand up or if the elevators will be too slow until the very end, after you’ve already spent millions of dollars on construction and materials.

Usually, to find out if your design "works" (specifically, if the electrical signals move fast enough), you have to run a massive, slow computer simulation called "synthesis." This is like building a miniature, expensive model of the skyscraper just to see if the stairs are too steep. It takes hours, or even days, and if you find a mistake, you have to start all over.

TimingLLM is like having a super-intelligent, instant building inspector who can look at your blueprints and tell you, "Hey, those elevators are going to be too slow," before you even buy a single brick.

Here is how this "Inspector" works, broken down into two stages:

Stage 1: The "Sketch Artist" (Reasoning)

Instead of just guessing, the first part of the AI acts like a detective. It reads your blueprints (the Verilog code) and writes a detailed "investigation report." It doesn't just say "it's slow"; it says, "I see a long hallway here, and the door at the end is too heavy, which will cause a delay."

It then turns this report into a "Digital Fingerprint." This fingerprint doesn't contain the actual code, but it captures the vibe of the design—how complex it is, how many "rooms" (gates) it has, and where the "traffic jams" (critical paths) are likely to happen.

Stage 2: The "Expert Consultant" (Retrieval & Steering)

Now, the second part of the AI takes over. This part is like a veteran engineer who has seen thousands of buildings before.

The Library Search (Retrieval): The AI takes that "Digital Fingerprint" from Stage 1 and runs to a massive library of past projects. It says, "Find me three buildings that have a similar fingerprint to this one."
The "Nudge" (Steering): This is the clever part. Instead of just reading the old projects, the AI uses them to "steer" its own thinking. Imagine you are trying to guess how much a house costs. If you see three similar houses nearby, you don't just add their prices together; you let their prices "nudge" your intuition in the right direction. In technical terms, the AI uses the "knowledge" from those similar past projects to fine-tune its own internal math, making its final guess much more accurate.

Why is this a big deal?

It’s Fast: It’s significantly faster than the old, heavy-duty simulation tools. It’s like getting an instant text message instead of waiting for a formal letter in the mail.
It’s Smart (and Accurate): It doesn't just guess; it reasons like a human engineer, which makes its errors much smaller.
It’s Adaptable: If you decide to change your building materials (switching "technology libraries") or if you want to see how the building handles a heatwave (changing "PVT corners"), you don't have to retrain the whole AI. You just give it a tiny bit of new information, and it learns the new rules almost instantly.

In short: TimingLLM turns a "wait-and-see" process into a "know-as-you-go" process, helping engineers build faster, better, and cheaper chips.

Technical Summary: TimingLLM

TimingLLM is a novel, two-stage retrieval-augmented Large Language Model (LLM) framework designed for the early prediction of post-synthesis timing metrics—specifically Worst Negative Slack (WNS) and Total Negative Slack (TNS)—directly from Verilog RTL code.

1. The Problem: The "RTL Timing Gap"

In the digital design flow, designers work at the Register-Transfer Level (RTL). However, accurate Static Timing Analysis (STA) can only be performed after synthesis and placement, processes that can take hours. This creates a feedback loop delay: designers often discover timing violations only after significant time has passed, hindering rapid architectural iteration and increasing time-to-market. Existing data-driven methods (like GNNs) often require heavy feature engineering, extensive retraining for different technology libraries, or fail to leverage existing repositories of labeled RTL.

2. Methodology: A Two-Stage Pipeline

The authors propose a pipeline that separates "timing reasoning" from "numerical regression," utilizing a retrieval-augmented approach to improve accuracy without leaking proprietary data.

Stage 1: Timing Reasoning & Fingerprinting
- Model: A fine-tuned Llama 3.1-8B model.
- Task: Instead of predicting numbers, Stage 1 is trained to generate a "synthetic STA report." It produces a human-readable "chain-of-thought" that identifies critical paths, local slacks, and intermediate node delays.
- Fingerprinting: The generated report is converted into an $\ell_2$ -normalized "structural–timing fingerprint." This fingerprint summarizes the design's timing context (e.g., gate counts, path depths, and topology) and is used to index a disjoint retrieval bank.
Stage 2: Retrieval-Guided Regression
- Model: A fine-tuned DeepSeek-R1-7B model with a small Multi-Layer Perceptron (MLP) head.
- Retrieval: Using the fingerprint from Stage 1, the system retrieves the $k$ -nearest neighbors from a disjoint retrieval bank ( $D_{rag}$ ).
- Diagonal Steering: This is a key innovation. Rather than simply appending neighbors as text tokens (which adds noise), the model calculates a "neighbor residual" from the last-layer activations of the retrieved modules. It then applies a learned diagonal steering vector ( $\gamma$ ) at the last transformer block of the query module. This "softly biases" the query's internal representation toward patterns observed in similar, previously labeled designs.
- Output: The steered representation is fed into the MLP to output the final WNS and TNS values.

3. Key Contributions

First Tool-Free Framework: Combines path-level STA reasoning with retrieval-guided regression for RTL timing.
Diagonal Steering Residual: Introduces a method to inject retrieval information directly into the transformer's latent space, preserving syntax and reducing noise.
Large-Scale Dataset: Curates and releases a 60k-module Verilog corpus with ground-truth WNS/TNS labels, enabling future research.
Efficient Adaptation: Demonstrates that the model can be adapted to new technology libraries or PVT (Process, Voltage, Temperature) corners by refitting only a tiny regression head (1,000 modules) rather than retraining the entire backbone.

4. Results

The framework was evaluated on the VerilogEval benchmark and compared against state-of-the-art (SOTA) methods like MasterRTL, RTL-Timer, and CircuitFusion.

Accuracy: TimingLLM achieved a Pearson correlation ( $R$ ) of 0.91 for WNS and 0.97 for TNS, with Mean Absolute Percentage Errors (MAPE) of 12% and 16%, respectively. This outperforms all baselines.
Speed: The end-to-end pipeline runs in approximately 323 seconds, making it faster than prior SOTA methods (which range from 411 to 514 seconds).
Robustness: Ablation studies confirmed that both stages are necessary; Stage 1 provides the reasoning context, while Stage 2 provides the numerical precision. The model also showed high stability across different libraries (Nangate45, Nangate15, ASAP7) and PVT corners.

5. Significance

TimingLLM represents a significant step toward "intelligent" EDA (Electronic Design Automation) tools. By enabling high-accuracy, near-instantaneous timing feedback at the RTL stage, it allows designers to catch critical timing violations during the architectural phase. Its ability to adapt to new manufacturing processes with minimal data makes it a highly practical solution for the rapidly evolving semiconductor industry.