Technical Summary: TREA – Low-Precision Time-Multiplexed, Resource-Efficient Edge Accelerator

Problem Statement

Edge Vision and Visual AI (EV2AI) systems, deployed on resource-constrained embedded platforms for tasks like object detection and scene recognition, face a fundamental trilemma among accuracy, latency, and energy consumption. State-of-the-art models, such as ViT-G, require billions of parameters and massive multiply-accumulate (MAC) operations, leading to prohibitive energy costs dominated by memory access (off-chip DRAM access can consume up to 640 pJ per access). Existing accelerator designs often address quantization, pruning, MAC unit design, or architectural reuse in isolation, lacking a unified co-design framework that spans the full algorithm-to-hardware stack. Furthermore, conventional MAC units suffer from accumulator bit-width expansion and high hardware overhead, while Non-Linear Activation Function (NAF) units can consume up to 25% of the total accelerator area.

Methodology

The paper proposes TREA, a unified edge-AI accelerator architecture that jointly optimizes arithmetic datapaths, pruning patterns, activation reuse, and layer-wise execution schedules. The methodology relies on three core co-designed components:

1. MSD-Guided Power-of-Two Quantization (MSD-PoTQ8) & DQ-MAC:
   The authors propose a multiplier-free Dual-Precision (4/8-bit) SIMD Multiply-Accumulate (DQ-MAC) unit. Instead of conventional multiplication, it utilizes a Most-Significant-Digit-First (MSDF) shift-and-add computation based on power-of-two decomposition.

   • Pre-accumulation Truncation: The scheme approximates weights using signed power-of-two terms. Crucially, it performs truncation before accumulation, reducing the required accumulator bit-width and eliminating post-multiplier quantization hardware.
   • Dual-Precision SIMD: The unit supports 4-bit or 8-bit fixed-point operations. Through digit-level time-multiplexing, a single hardware instance can execute four 4-bit operations or one 8-bit operation per cycle, achieving up to 4x throughput without hardware duplication.

2. Structured Hardware-Aware Reductive Pruning (SHARP):
   To maximize the utilization of the 4-lane SIMD datapath, the authors introduce SHARP, a pruning strategy that aligns sparsity patterns directly with hardware execution granularity.

   • Alignment: Unlike standard structured pruning, SHARP enforces kernel-wise weight retention ratios (4:9 for 3x3 kernels and 12:25 for 5x5 kernels) that are exact multiples of the SIMD width.
   • Scheduling: This alignment ensures full lane utilization, eliminating partially occupied execution cycles and transforming pruning into a hardware-efficient scheduling mechanism.

3. Reconfigurable Quantise-enabled Non-Linear Activation (RQ-NAF):
   A single, shared CORDIC-based core implements Sigmoid, Tanh, and ReLU functions.

   • Time-Multiplexing: Rather than instantiating separate hardware for every neuron or layer, a single 9-stage pipelined RQ-NAF core is time-multiplexed across the network.
   • Efficiency: After an initial pipeline fill, it produces one output per cycle, significantly reducing area overhead while supporting runtime selection of activation functions.

The complete TREA architecture integrates a 1D array of 100 SIMD DQ-MAC units with the shared RQ-NAF core, controlled by a unified engine that manages layer-wise hardware reuse and tiling.

Key Contributions

The paper details the following specific contributions:

• DQ-MAC Unit: A multiplier-free, MSDF-based SIMD MAC that performs pre-accumulation truncation, reducing accumulator width and enabling 4x throughput improvement via 4-bit SIMD execution without hardware duplication.
• SHARP Strategy: A co-design pruning method that maps sparsity patterns (4:9 and 12:25) to the SIMD width, guaranteeing 100% lane utilization and reducing kernel execution cycles (e.g., 3x3 kernels from 9 cycles to 1 cycle in 4-bit mode).
• RQ-NAF Core: A reconfigurable, time-multiplexed CORDIC-based activation unit that supports multiple functions (ReLU, Sigmoid, Tanh) with (N-1) hardware reuse, drastically cutting activation hardware overhead.
• System-Level Co-Design: A unified 1D accelerator architecture that integrates DQ-MAC, SHARP, and RQ-NAF, validated through FPGA implementation and 28-nm ASIC synthesis.

Results

The TREA accelerator was evaluated using YOLO variants for object detection (PASCAL VOC, COCO) and MobileNet/EfficientNet/Inception for classification (ImageNet), alongside hardware synthesis on Xilinx VC707 FPGAs and 28-nm ASIC processes.

• Accuracy: The system maintains detection accuracy comparable to FP32 baselines, with less than 3% mAP@0.5 degradation across YOLO variants. The dual-precision configuration achieves accuracy comparable to 8-bit uniform quantization while selectively operating at 4-bit precision.
• Latency & Throughput: The combination of SHARP and DQ-MAC yields up to a 9x latency reduction at the kernel level (e.g., 3x3 kernels computed in 1 cycle vs. 9 cycles). The accelerator achieves up to 4x throughput improvement over fixed-precision designs.
• Hardware Efficiency:
  • FPGA: Compared to Xilinx IP cores, the DQ-MAC reduces LUT utilization by up to 72% and power consumption by up to 50%.
  • ASIC: The design demonstrates competitive area, delay, and Power-Delay Product (PDP) compared to state-of-the-art approximate MAC units, offering a more compact and balanced implementation for embedded systems.
  • Resource Footprint: TREA achieves one of the lowest resource footprints (LUTs and registers) among compared domain-specific accelerators while maintaining high energy efficiency (GOPS/W).

Significance

The paper claims that TREA represents a significant step forward by moving beyond isolated optimizations to a holistic algorithm–hardware co-design framework. Its significance lies in:

1. Unified Optimization: It successfully integrates quantization, structured pruning, and architectural reuse into a single pipeline, ensuring that model-level optimizations (like pruning) directly translate to hardware efficiency (full SIMD utilization).
2. Resource Efficiency: By eliminating multipliers and reusing activation hardware via time-multiplexing, TREA addresses the stringent area and power budgets of edge platforms, making real-time object detection and classification feasible on battery-powered devices.
3. Scalability: The time-multiplexed 1D architecture allows for scalable deployment across varying DNN topologies without replicating dedicated hardware per layer, reducing control complexity and silicon area.

The authors conclude that TREA provides a practical, scalable solution for real-time edge vision workloads, validating its effectiveness through comprehensive FPGA and ASIC evaluations against state-of-the-art designs.