💻 computer science

Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

This paper presents a hardware-software co-design approach using Bistable Memory Recurrent Units (BMRUs) to overcome noise accumulation barriers, enabling ultra-low power, scalable analog recurrent neural networks for always-on AI applications that achieve sub-microwatt inference with high-fidelity circuit-to-software correspondence.

Original authors: Arthur Fyon, Julien Brandoit, Loris Mendolia, Damien Ernst, Jean-Michel Redouté, Guillaume Drion

Published 2026-05-18

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CC BY 4.0

Original authors: Arthur Fyon, Julien Brandoit, Loris Mendolia, Damien Ernst, Jean-Michel Redouté, Guillaume Drion

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you have a tiny, battery-powered device that needs to listen to the world 24/7—like a smart sensor in a forest or a medical implant in your body. The problem is that batteries are heavy and need frequent changing. To make these devices last for years, they need to use almost no electricity.

For a long time, engineers thought there was a hard limit: you could make a device that listens and reacts (like saying "Yes!") using very little power, but you couldn't make it remember things over time (like understanding a sentence) without using a lot of energy. It was like trying to build a house out of sand; the moment you tried to add a second floor (memory), the whole thing would collapse under the weight of "noise" (static and errors).

This paper presents a new way to build these devices using a mix of clever math and custom-made electronics. Here is how they did it, explained simply:

1. The Problem: The "Sandcastle" of Memory

Think of a standard digital computer as a very precise accountant. It counts everything perfectly, but it takes a lot of energy to move the numbers around.
Think of an analog circuit (the kind this paper uses) as a flowing river. It's incredibly energy-efficient, but if you try to send a message downstream and then loop it back upstream (recurrence), the water gets muddy. The signal gets distorted by "noise" (like a whisper getting lost in a windstorm) every time it loops. Eventually, the message becomes gibberish. This is why scientists thought you couldn't build a memory-based AI with ultra-low power analog circuits.

2. The Solution: The "Bistable Switch"

The authors found a special type of mathematical building block called a Bistable Memory Recurrent Unit (BMRU).

The Analogy: Imagine a light switch that doesn't just turn on or off, but has a "sticky" middle.
- If you push the switch slightly, it snaps back to where it was (ignoring small bumps).
- Only if you push it hard does it snap to the other side and stay there.
Why it helps: Because the switch only has two stable positions (On or Off), it ignores the "muddy water" (noise). Even if the signal gets a little distorted on its way back, the switch just snaps back to its clear "On" or "Off" state. This stops the noise from piling up.

3. The Magic Trick: Hardware-Software Co-Design

Usually, software engineers write code, and hardware engineers build chips to run that code. They often don't match perfectly.
In this paper, the team did Co-Design. They didn't just write code and then try to build a chip for it. Instead, they designed the math specifically to match the physics of a tiny electronic switch they built from scratch.

The Result: Every single number in their software model (like a weight or a threshold) maps directly to one specific physical part of the chip (like the width of a transistor or a specific current). It's like having a blueprint where every line drawn on paper corresponds exactly to a brick in the wall.

4. The "First Quadrant" Fix

The math they used originally required signals to go both positive and negative (like a thermometer going above and below zero). But their tiny, low-power chips only handle positive signals (like a water flow that can only go forward).
They invented a new version called the First-Quadrant BMRU.

The Analogy: Instead of a seesaw that goes up and down, they built a system that only moves forward or stays still. They proved mathematically that this "one-way" system can do the exact same memory tasks as the "up-and-down" system, just by rearranging the math slightly. This allowed them to build the circuit using only simple, energy-efficient parts.

5. The Proof: The "Yes" Detector

To prove it worked, they built a tiny chip (in a simulation) designed to listen for the word "Yes" in a noisy room.

The Chip: It was made of 768 tiny transistors, all operating at a power level so low it's measured in nanowatts (billionths of a watt).
The Test: They ran the chip through thousands of audio clips.
The Result: The chip's behavior matched the computer software prediction almost perfectly. It correctly identified the word "Yes" while using less than 100 nanowatts of power.
Noise Immunity: When they added artificial noise to the simulation (simulating a bad connection or a manufacturing defect), the chip kept working. The "sticky switch" design successfully blocked the noise, proving that memory can exist in ultra-low-power analog circuits without collapsing.

Summary

The paper shows that by designing the math and the physical chip together, and by using a "sticky switch" mechanism that ignores small errors, they have built the first analog brain that can remember things over time while using almost no energy. They demonstrated this by creating a chip that can listen for a specific word, proving that "always-on" AI devices could one day run for years on a tiny battery.

Technical Summary: Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

Problem Statement

Always-on Artificial Intelligence (AI) applications, such as environmental sensors and biomedical implants, demand ultra-low power consumption, often in the sub-microwatt range. While analog circuits offer a pathway to achieve this efficiency, existing analog implementations are largely restricted to feedforward architectures. Extending these to recurrent dynamics has historically been deemed impractical due to the accumulation of analog noise through temporal feedback loops. Furthermore, current digital edge AI solutions (e.g., TinyML on microcontrollers) operate at milliwatt levels, orders of magnitude higher than what subthreshold analog circuits can theoretically achieve. There is a lack of architectures that simultaneously support parallelizable training, multistable memory, analog computation, and sub-microwatt power consumption.

Methodology

The authors propose a hardware-software co-design approach centered on Bistable Memory Recurrent Units (BMRUs), a class of Recurrent Neural Networks (RNNs) characterized by discrete-valued outputs and hysteretic dynamics. The methodology proceeds in three key steps:

Algorithmic Reformulation (First-Quadrant BMRU):
The standard BMRU formulation, which relies on bipolar outputs and input-dependent thresholds, is incompatible with simple, unipolar current-mode analog circuits. The authors reformulate the BMRU into a First-Quadrant (FQ) BMRU. This variant operates entirely with non-negative values, utilizing fixed thresholds ( $\beta_{lo}, \beta_{hi}$ ) learned during training but constant during inference. This reformulation enables a direct mapping to single-ended current-mode circuits without the need for differential pairs or negative power supplies, while preserving the expressivity and trainability of the original model.
Circuit Implementation:
A custom ultra-low power current-mode analog circuit is designed from first principles to implement the FQ BMRU.
- Current-Mode Operation: All signals are represented as currents, leveraging the exponential I-V relationship of subthreshold MOS transistors for natural dynamic range compression and picoampere-level operation.
- Transistor-Only Design: The circuit eliminates resistors, capacitors, and inductors, achieving true monolithic integration. The instantaneous convergence of the BMRU removes the need for on-chip capacitors required by traditional RNNs or State-Space Models (SSMs).
- One-to-One Mapping: Every learned parameter maps directly to a specific circuit element. Weights correspond to transistor width ratios in current mirrors, while thresholds and gains correspond to bias currents.
- Bistable Cell: The core cell is a 9-transistor current-mode Schmitt trigger that implements hysteresis. It features independent programmability of the high switching point ( $I_{thresh}$ ), output amplitude ( $I_{gain}$ ), and hysteresis width ( $I_{width}$ ).
Validation Pipeline:
The network is trained entirely in software using JAX/Flax. The learned parameters are then mapped to transistor dimensions and bias currents for inference in Cadence Spectre transistor-level simulations using X-FAB 180 nm CMOS technology. This high-fidelity software model serves as a proxy for the physical hardware, enabling large-scale noise and power analyses that would be computationally prohibitive at the transistor level.

Key Contributions

The paper claims four primary contributions:

One-to-One Hardware-Software Correspondence: The FQ BMRU formulation ensures that each learned parameter maps to a single, programmable circuit element. Transistor-level simulations confirm near-perfect agreement between software predictions and circuit dynamics at every intermediate signal stage.
Structural Noise Immunity: The discrete-valued outputs of the BMRU act as a structural barrier against analog noise. At each cell boundary, the hysteretic thresholding suppresses accumulated analog noise by at least 20-fold, breaking the noise accumulation barrier that has historically prevented analog recurrence.
Recurrence at Low Marginal Cost: Power scaling analysis reveals that while feedforward layers (fully connected) scale quadratically with state dimension, the BMRU recurrence layers scale linearly. Consequently, adding temporal processing capabilities to an analog feedforward backbone incurs only a small, linearly-scaling marginal power cost.
Sub-Microwatt Operation: The RNN core of a minimal proof-of-concept network achieves approximately 100 nW power consumption during continuous inference, operating entirely in the subthreshold regime with clockless, continuous-time dynamics.

Results

The authors validate their approach through several benchmarks and simulations:

Keyword Spotting (KWS): On the Google Speech Commands dataset (specifically the "yes" vs. others task), the analog implementation achieves 98.08% accuracy in software and 96.98% in transistor-level simulation for a state dimension of $d=16$ . For the minimal $d=4$ configuration used for hardware validation, hardware predictions matched software predictions in 49 out of 50 test cases, with the single discrepancy occurring at a decision boundary tie.
Noise Robustness: Large-scale noise analysis across sMNIST, pMNIST, and dKWS benchmarks demonstrates that the FQ BMRU maintains full accuracy at measured analog noise levels, whereas linear recurrent units (LRU) fail catastrophically. The FQ BMRU remains robust up to approximately 2 $\times$ the measured analog noise magnitude.
Power Efficiency: At $d=4$ , the RNN core consumes ~100 nW. Power breakdown analysis shows that as state dimension increases, the relative power contribution of the recurrent cells decreases compared to the feedforward layers, confirming the linear marginal cost of recurrence.
Generalization: The approach generalizes to multi-class digit recognition (11 classes) with competitive accuracy and improved output margin separation, remaining within sub-microwatt estimates.

Significance and Claims

The paper claims to present the first fully analog RNN implementation that combines structural noise immunity with parallelizable training. By demonstrating that discrete-valued, hysteretic dynamics can be mapped to ultra-low power current-mode circuits, the authors argue that the barrier to analog recurrence has been overcome.

The significance of this work lies in its potential to enable always-on edge AI with temporal processing capabilities at power levels previously unattainable for recurrent architectures. The authors posit that any existing or future analog feedforward platform could, in principle, gain temporal intelligence by integrating BMRU cells at a minimal additional power cost. This co-design approach bridges the gap between algorithmic requirements for persistent memory and the physical constraints of subthreshold analog hardware, offering a path toward energy-efficient, continuous-time inference for applications like environmental monitoring and biomedical implants.

The authors remain modest regarding limitations: the results are currently validated via transistor-level simulation in 180 nm CMOS and await physical fabrication. Furthermore, while multi-class and complex benchmarks are evaluated in software with realistic noise models, hardware validation is currently focused on binary keyword spotting.