Cooling Channel Design Optimization for High Power Multi-chip Packages

Technical Summary: Cooling Channel Design Optimization for High Power Multi-Chip Packages

Problem Statement
Modern high-performance computing systems, particularly heterogeneous multi-chip packages like the NVIDIA GB200 Grace Blackwell Superchip, face critical thermal management challenges due to increasing power densities in GPUs and AI accelerators. Traditional cooling methods are often insufficient for the high heat fluxes generated, and existing computational studies frequently rely on simplified thermal models that fail to explicitly represent coolant transport within channel networks. This omission can lead to inaccurate predictions of thermal non-uniformity and hotspot formation, especially in geometries where coolant connectivity directly impacts thermal performance. The specific challenge addressed in this work is the optimization of embedded microchannel layouts for a representative multi-chip package (two GPUs and one CPU) to minimize peak and average chip temperatures while maintaining physical realism regarding coolant heating and distribution.

Methodology
The authors developed a physics-based computational framework that couples steady-state in-plane heat conduction with a reduced-order representation of coolant transport. The methodology involves the following key components:

• Thermal Model: The substrate temperature is governed by a steady-state energy balance equation coupling conduction with convective heat removal. The effective heat transfer coefficient is spatially variable, applying enhanced cooling only within channel regions while maintaining a weak background cooling level across the substrate.
• Coolant Transport: To capture the thermal evolution of the fluid without the computational cost of full 3D CFD, the model employs a row-wise coolant energy balance. As the fluid flows through the manifold, its temperature is updated based on the heat absorbed from the substrate in preceding rows, ensuring that the reduced cooling capacity of warmer fluid near the outlet is accounted for.
• Design Parameterization: The cooling architecture is defined as an interdigitated layout parameterized by three geometric variables: the number of channels ($N$), channel width ($W$), and the expansion width over chip regions ($E$). The design space is constrained to ensure symmetry and physical realizability (e.g., expansion width must be greater than or equal to channel width).
• Optimization Strategy: Due to the non-linear coupling between heat conduction and fluid transport, direct optimization is computationally prohibitive. The authors employ a surrogate-based approach. A full-factorial design of experiments (116 candidate designs) is simulated using the full physics-based solver. These results train quadratic surrogate models to approximate the relationship between geometric parameters and thermal metrics ($T_{max}$ and $T_{avg}$). The optimization problem is then solved using a Mixed-Integer Quadratic Programming (MIQP) algorithm via the Gurobi Optimizer to minimize a weighted objective function prioritizing peak temperature reduction.

Key Contributions
The paper claims two primary contributions:

1. The development of a coupled thermal model that integrates steady-state heat conduction with a reduced-order coolant transport representation specifically tailored for multi-chip systems.
2. The establishment of an optimization-driven channel design framework that identifies cooling layouts capable of significantly reducing peak and average chip temperatures under realistic operating conditions, moving beyond fixed channel layouts to a parametric, optimization-based approach.

Results
The framework was applied to a 120 mm × 120 mm substrate containing two GPUs (1200 W each) and one CPU (300 W).

• Baseline Performance: A symmetric manifold-fed configuration with moderate channel width and limited expansion yielded a maximum chip temperature ($T_{max}$) of 220.36°C and an average temperature ($T_{avg}$) of 102.14°C.
• Optimized Performance: The MIQP algorithm identified an optimal configuration with 7 channels, a width of 4 mm, and an expansion width of 28 mm. This design achieved a $T_{max}$ of 79.91°C and a $T_{avg}$ of 66.27°C.
• Improvement: Compared to the baseline, the optimized design reduced the peak temperature by 140.45°C and the average temperature by 35.87°C.
• Physical Relevance: The optimized design maintains temperatures well below the recommended 95°C operating limit for high-performance processors. The results highlight that increasing cooling coverage specifically near GPU regions (via channel expansion) is the dominant factor in hotspot mitigation, while balanced flow distribution remains critical for overall uniformity. The surrogate models demonstrated high accuracy with Root Mean Square Errors (RMSE) of 8.051°C for $T_{max}$ and 2.442°C for $T_{avg}$.

Significance
The authors position this work as providing a "practical and extensible approach" for topology-aware cooling design in advanced electronic packaging systems. The significance lies in demonstrating that combining reduced-order thermal modeling with mathematical optimization can effectively identify cooling topologies that drastically improve thermal performance without the prohibitive cost of full CFD-based optimization. The study validates that systematic design exploration, constrained by physical relevance (such as coolant heating and localized expansion), can yield designs that meet the stringent thermal requirements of next-generation heterogeneous computing packages. The authors note that future work could extend this framework to higher-fidelity CFD validation, transient analysis, and larger data-center-scale systems.