💻 computer science

OpenOpt: An Open-Source SRAM Optimizer Based on Equivalent Circuit Model

This paper introduces OpenOpt, an open-source co-optimization framework that leverages equivalent circuit models to jointly optimize SRAM architecture and transistor sizing, achieving significant simulation speedups and superior performance metrics compared to existing methods.

Original authors: Yikai Wang, Yiheng Wu, Can Wang, Bohao Liu, Junhao Ma, Zhuohua Liu, Qinxin Mei, Shan Shen

Published 2026-06-09

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CC BY 4.0

Original authors: Yikai Wang, Yiheng Wu, Can Wang, Bohao Liu, Junhao Ma, Zhuohua Liu, Qinxin Mei, Shan Shen

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to design the ultimate storage locker for a massive warehouse. This isn't just any warehouse; it's the brain of a modern computer chip, where billions of tiny memory cells (SRAM) hold all the data. The goal is to make these lockers as fast, small, and energy-efficient as possible without them falling apart.

For a long time, designing these memory banks was like trying to solve a giant jigsaw puzzle by hand, piece by piece, using only guesswork and experience. It took forever because every time you changed the size of one tiny screw (a transistor), you had to simulate the entire warehouse to see if it still worked.

The paper introduces OpenOpt, a new tool that acts like a "super-smart architect" to solve this puzzle much faster and better. Here is how it works, broken down into simple concepts:

1. The "Magic Shortcut" (The Equivalent Circuit Model)

The biggest problem with the old way was speed. Simulating a warehouse with millions of lockers using a high-precision physics engine (called SPICE) is incredibly slow. If you have a million lockers, the computer has to check every single one, even the ones you aren't currently using.

The Innovation: The authors realized that when you aren't using a specific locker, it doesn't need to be simulated in full detail. It just acts like a tiny weight or a small electrical "drag" on the system.

The Analogy: Imagine you are testing the traffic flow in a city. Instead of simulating every single car in the city (millions of them), you only simulate the cars on the main road you are testing. For all the other cars parked in garages or on side streets, you just replace them with a simple "traffic weight" that accounts for their presence without needing to drive them around.
The Result: This "shortcut" makes the simulation 61 times faster (like going from a slow walk to a supersonic jet) while still being incredibly accurate (less than 2% error).

2. The "Two-Pronged" Strategy (Co-Optimization)

Previously, designers would either change the layout of the warehouse (how many rows and columns of lockers) OR they would tweak the size of the screws inside the lockers. They rarely did both at the same time because it was too complicated.

The Innovation: OpenOpt looks at both problems simultaneously.

The Analogy: Think of it like designing a house. You can't just decide "I want bigger windows" (transistor sizing) without thinking about "Do I want a mansion or a cottage?" (architecture). If you pick a mansion but use tiny windows, it's inefficient. If you pick a cottage but use giant windows, it's unstable. OpenOpt finds the perfect balance between the shape of the house and the size of the windows all at once.

3. The "Tournament of Algorithms"

To find the best design, the tool uses seven different "search strategies" (algorithms). Think of these as seven different teams of explorers trying to find the treasure in a dark forest.

Some teams are cautious and methodical (like Simulated Annealing).
Some teams swarm together like a flock of birds (Particle Swarm Optimization).
Some teams use complex maps to predict where the treasure might be (Bayesian Optimization).
The Winner: One team, called MOEA/D, turned out to be the champion. It found a design that was:
- 73.6% smaller (saving massive space).
- 42.3% more energy-efficient (using less power).
- 6.2% more stable (less likely to lose data).

4. The "Aha!" Moment (What Actually Matters?)

The researchers did a special test to see which part of the process mattered more: changing the layout or changing the screw sizes.

The Finding: Changing the layout (the architecture) did about 84% of the heavy lifting. It was like realizing that building a few large, efficient rooms was far better than building thousands of tiny, cramped closets.
The Refinement: Changing the screw sizes (transistor sizing) provided the final polish, squeezing out the last bits of efficiency.
The Lesson: You need both, but getting the big picture right first is the most important step.

Summary

OpenOpt is an open-source tool that helps engineers design computer memory much faster and better than before. It does this by:

Using a "smart shortcut" to simulate millions of memory cells in seconds instead of hours.
Simultaneously adjusting the big layout and the tiny internal components.
Using a team of smart algorithms to find the perfect balance, resulting in memory that is smaller, faster, and uses less power.

The paper concludes that this tool is now available for anyone to use, helping to build the next generation of faster and more efficient chips.

Technical Summary: OpenOpt – An Open-Source SRAM Optimizer Based on Equivalent Circuit Model

1. Problem Statement

As semiconductor process nodes scale down, Static Random Access Memory (SRAM) design faces critical challenges in balancing Power, Performance, and Area (PPA) against yield. Traditional design flows rely heavily on manual iteration and high-precision SPICE simulations, which become computationally prohibitive for large-scale arrays containing millions of cells. The runtime of full-array SPICE simulation grows super-linearly with array size, creating a bottleneck for optimization.

Furthermore, existing optimization approaches often suffer from two limitations:

Simulation Efficiency: Surrogate models (e.g., neural networks) lack physical interpretability and struggle with accuracy under sparse sampling or boundary conditions, while prior analytical models often neglect power modeling and inter-transistor coupling.
Decoupled Optimization: Many frameworks treat architecture-level configuration (row/column counts, multiplexing ratios) and transistor-level sizing as separate, sequential stages. This decoupling prevents the discovery of globally optimal solutions within the joint design space, as architecture choices significantly impact the efficacy of transistor sizing and vice versa.

2. Methodology

The paper proposes OpenOpt, a co-optimization framework that jointly optimizes SRAM architecture and transistor sizing using a high-fidelity equivalent circuit model. The workflow consists of three core components:

A. Equivalent Circuit Model for Simulation Acceleration

To address the simulation bottleneck, the authors replace inactive SRAM cells with compact equivalent RC loads and static power models.

Hierarchical Modeling: A 3×3 array model is constructed where the central cell is a full 6T SRAM, and the surrounding 8 cells are replaced by equivalent circuits.
Component Simplification:
- Bit Lines (BL/BLB): Modeled as pure capacitance ( $C_{BL}$ ) for unselected rows, as access transistors are off.
- Word Lines (WL): Modeled with a simplified single-capacitance approach ( $C_{WL}$ ) that captures the dominant behavior without complex RC networks.
- Static Power: Modeled as a resistance ( $R_{static}$ ) derived from cell-level simulation.
Scalability: The model extends to arbitrary $m \times n$ arrays via linear superposition, ensuring computational complexity remains decoupled from array size.
Architecture Penalties: The framework analytically models penalties for chip-select decoding (logarithmic delay based on sub-array count) and column multiplexing (delay and power based on multiplexing ratio), ensuring the optimizer accounts for peripheral overhead.

B. Joint Search Space and Optimization Algorithms

OpenOpt defines a unified search space encompassing:

Architecture Parameters: Number of rows ( $r$ ), columns ( $c$ ), multiplexing ratio ( $\mu$ ), and number of sub-arrays ( $n_a$ ), constrained by total capacity.
Transistor Parameters: Widths ( $W_{PU}, W_{PD}, W_{PG}$ ), lengths ( $L$ ), and threshold voltages ( $V_{th}$ ).

The framework integrates seven optimization algorithms to navigate this space:

Single-Objective: Simulated Annealing (SA), Particle Swarm Optimization (PSO), Constrained Bayesian Optimization (CBO), SMAC, and RoSE-Opt. These maximize a composite Figure of Merit (FoM).
Multi-Objective: NSGA-II and MOEA/D. These directly optimize SNM, Power, Delay, and Area to explore the Pareto front.

C. Evaluation Metric

For single-objective algorithms, a comprehensive FoM is calculated:
$\text{FoM} = \log_{10} \left( \frac{\text{SNM}_{\min}}{\text{Power}_{\max} \times \text{Delay}_{\max} \times \sqrt{\text{Area}}} \right)$
Multi-objective algorithms utilize raw metrics to generate Pareto-optimal trade-offs.

3. Key Contributions

High-Fidelity Equivalent Circuit Model: A model that replaces inactive cells with RC loads, achieving up to 61.4× simulation speedup while maintaining high accuracy (read/write delay error < 0.22%, power error < 1.68%).
Unified Co-Optimization Platform: A framework that simultaneously explores architecture and transistor sizing, demonstrating through ablation studies that these two stages provide complementary gains rather than redundant improvements.
Open-Source Toolchain: Integration of five single-objective and two multi-objective algorithms, released publicly to support the SRAM design community.

4. Experimental Results

Experiments were conducted using the FreePDK45 process node with a target capacity of 32 KB × 8 (262,144 bits).

Simulation Accuracy: The equivalent circuit model showed negligible error compared to full SPICE simulations across various array sizes (32×16 to 512×512), with power errors capped at 1.68%.
Algorithm Performance: Among the seven algorithms tested, MOEA/D achieved the best Figure of Merit (8.2721).
- Improvements over Unoptimized Baseline:
  - Area: Reduced by 73.6% (from 0.4773 mm² to 0.1253 mm²).
  - Peak Power: Reduced by 42.3%.
  - SNM (Stability): Improved by 6.2% (0.273 V to 0.290 V).
  - Delay: Read and write delays improved by 11.3% and 14.9%, respectively.
Ablation Study (Architecture vs. Sizing):
- Architecture Selection (Stage 0→1): Consolidating 1024 small sub-arrays into 128 medium-sized arrays contributed ~84% of the total FoM gain, primarily by reducing peripheral overhead (decoders, sense amplifiers, routing).
- Transistor Sizing (Stage 1→2): Provided complementary refinements, further reducing area by 16.6% and improving SNM by 6.3% by tuning pull-up/pull-down ratios and threshold voltages.

5. Significance and Claims

The paper claims that OpenOpt addresses the critical bottlenecks of simulation efficiency and decoupled design in SRAM optimization. By leveraging an equivalent circuit model, the framework enables the exploration of a joint architecture-sizing space that was previously computationally intractable.

The authors emphasize that the co-optimization strategy is essential; neither architecture selection nor transistor sizing alone can achieve the global optimum. The results validate that architecture reorganization provides the bulk of the efficiency gains, while transistor sizing offers necessary fine-tuning. The public release of the toolchain aims to facilitate further research and adoption of automated SRAM design optimization.