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Electrothermal behavior of superconducting nanowires buried in a commercial CMOS process

This paper investigates the electrothermal behavior of titanium nitride nanowires buried within a commercial 22 nm FD-SOI CMOS process, revealing that their retrapping currents are governed by a two-channel cooling model combining interfacial phonon emission and longitudinal conduction, with an effective cooling coefficient significantly lower than theoretical predictions for clean interfaces.

Original authors: Mohamed Gharib, Leonid Popryho, Salma Abdelzaher, Tejas Guruswamy, Tomas Polakovic, Umeshkumar Patel, Orlando Quaranta, Thomas Cecil, Clarence Chang, Yu-Sheng Chen, Thomas H. Swift, Grayson M. Noah, A

Published 2026-09-29

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CC BY 4.0

Original authors: Mohamed Gharib, Leonid Popryho, Salma Abdelzaher, Tejas Guruswamy, Tomas Polakovic, Umeshkumar Patel, Orlando Quaranta, Thomas Cecil, Clarence Chang, Yu-Sheng Chen, Thomas H. Swift, Grayson M. Noah, Alberto Gomez-Saiz, John J. L. Morton, M. Fernando Gonzalez-Zalba, Antonino Miceli, Inna Partin-Vaisband

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the world of modern electronics, the most powerful computers are built on silicon chips that operate at room temperature, but the most sensitive detectors for light and the most advanced quantum computers often require temperatures near absolute zero. For years, scientists have dreamed of combining these two worlds: placing delicate superconducting sensors directly onto the same silicon chip that controls them, eliminating the need for bulky, complex wiring between a cold detector and a warm computer. The challenge has been finding a material that can act as a superconductor in these extreme cold conditions while also being compatible with the standard manufacturing processes used to make everyday computer chips. It turns out that the very materials used to build modern chips—specifically thin films of titanium nitride used as barriers and connectors—can become superconductors when cooled down, offering a hidden path to this integration. However, simply knowing a material can superconduct is not enough; engineers need to understand exactly how heat moves through these tiny, buried wires when they are forced to carry an electric current, because heat is the enemy of superconductivity.

A team of researchers has now mapped out exactly how heat behaves in these hidden wires, revealing a surprising weakness in the cooling system that could actually be useful for building new types of computer memory and logic. The scientists studied tiny wires made of titanium nitride, which are buried deep inside a standard commercial computer chip, sandwiched between layers of metal and insulating glass. When electricity flows through these wires, they can suddenly switch from a state of zero resistance to a state where they resist the flow, creating a hot spot. The researchers wanted to know how much current it takes to keep this hot spot alive once it has formed, a value known as the retrapping current. If the wire cools down too efficiently, the hot spot collapses and the wire returns to being a superconductor; if it cools too slowly, the hot spot grows uncontrollably. By measuring this behavior across different wire lengths and temperatures, the team discovered that the heat does not escape the way most engineers expected.

The researchers found that for long wires, the heat escapes primarily by traveling vertically out of the wire and into the surrounding layers of the chip, rather than flowing along the wire to the metal contacts at the ends. This vertical cooling is surprisingly inefficient. The team measured a cooling coefficient that is roughly thirty times lower than what would be expected for a clean, single interface between two materials, and about twelve times lower than the best cooling rates seen in similar nanowires in other studies. This inefficiency means the wires hold onto heat much longer than anticipated. Because the heat is trapped so effectively, the wires can sustain a stable hot spot with a relatively small amount of current. This stability is crucial for devices that rely on hysteresis, where the state of the device depends on its history, such as in superconducting memory or logic gates.

The study also explored how the length of the wire changes this behavior. In very short wires, the heat can reach the ends and escape through the contacts, but as the wires get longer, the vertical cooling into the surrounding stack becomes the dominant factor. The researchers identified a specific crossover point, around 3.5 micrometers in length, where the behavior shifts from being controlled by the contacts to being controlled by the surrounding layers. This crossover length is much larger than what would be predicted if the cooling were efficient, confirming that the buried environment acts as a thermal bottleneck. The team ruled out the idea that heat travels primarily along the wire to the contacts for these lengths, showing instead that the vertical path is the main route for heat loss, albeit a slow one.

These findings provide a clear picture of the electrothermal landscape for superconducting devices built into standard computer chips. The researchers established that the titanium nitride films, which are incidental byproducts of the chip-making process, are robust enough to support the hot spots needed for advanced superconducting circuits. The unusually low cooling rate means that these buried wires can maintain their resistive state with less energy than previously thought, making them viable candidates for integration with cryogenic electronics. The work confirms that the geometry of the chip stack, with its layers of metal and glass, creates a unique thermal environment that can be modeled and predicted. This understanding allows engineers to design superconducting detectors and logic circuits that are monolithically integrated with their control electronics, paving the way for more compact and powerful quantum computing systems without the need for complex external cooling infrastructure.

Technical Summary: Electrothermal Behavior of Superconducting Nanowires Buried in a Commercial CMOS Process

Problem Statement
Commercial complementary metal-oxide-semiconductor (CMOS) processes utilize transition-metal nitrides and silicides as diffusion barriers and liner metals. At cryogenic temperatures, these films, specifically titanium nitride (TiN) within polycrystalline-silicon resistors, exhibit superconductivity. While recent work has exploited this for high-kinetic-inductance "superinductors," the electrothermal behavior of these films when buried beneath the back-end-of-line (BEOL) metal stack remains uncertain. In superconducting nanowire detectors and logic, the ability to sustain a self-heated normal (resistive) hot spot is critical. However, the dense dielectric and metal environment of a commercial process (encapsulated in amorphous dielectric with oxide below and metal interconnects above) may quench such hot spots via enhanced cooling. The specific mechanisms governing heat removal—whether dominated by longitudinal conduction to contacts or vertical interfacial cooling into the stack—and the resulting retrapping currents ( $I_r$ ) require experimental characterization and modeling to determine if these films are viable for monolithic integration of detectors and logic with cryogenic CMOS electronics.

Methodology
The study utilized TiN nanowires fabricated within the front-end-of-line (FEOL) of a GlobalFoundries 22 nm fully depleted silicon-on-insulator (FD-SOI) process. The TiN film, approximately 3 nm thick, is buried beneath the BEOL stack.

Device Fabrication: Nanowires were defined with lengths ( $\ell$ ) ranging from 1 to 50 $\mu$ m and widths ( $W$ ) of 0.50 $\mu$ m and 1.00 $\mu$ m.
Measurement: Four-point current–voltage ( $I$ – $V$ ) characteristics were measured at bath temperatures ( $T_b$ ) ranging from 0.15 K to 1.19 K. The switching current ( $I_{sw}$ ) and retrapping current ( $I_r$ ) were extracted from hysteretic loops.
Modeling: The authors compared experimental $I_r$ $I_{r}$ data against two theoretical limits:
1. Longitudinal Conduction: Heat flow along the wire to the contacts, scaling as $I_r \propto \ell^{-1}$ .
2. Interfacial Cooling: Vertical phonon-mediated heat flux into the surrounding stack, scaling as $I_r \propto \ell^0$ (length independent) with a temperature dependence of $(T_{hs}^n - T_b^n)^{1/2}$ .
3. Two-Channel Model: A phenomenological interpolation combining both mechanisms using a thermal healing length ( $\eta$ ) and a crossover length ( $\ell^*$ ).

Key Results

Hysteresis and Stability: The nanowires exhibit strong hysteresis with switching-to-retrapping current ratios ( $I_{sw}/I_r$ ) between 7.4 and 9.8, confirming the ability to sustain self-heated hot spots despite the buried environment.
Cooling Mechanism: For long wires ( $\ell = 50$ $\mu$ m), $I_r$ follows the interfacial cooling form $(T_{hs}^n - T_b^n)^{1/2}$ with an exponent $n \approx 4$ (consistent with phonon-radiation models) rather than the $n=1$ expected for constant thermal conductivity longitudinal conduction. Free-exponent fits yielded $n \approx 4.8–5.0$ .
Cooling Coefficient: The effective interfacial cooling coefficient ( $\Sigma_K$ ) was extracted as $7.9(3)$ W/(m $^2$ K $^4$ ). This value is approximately 31 times lower than the acoustic-mismatch prediction for a single clean TiN/SiO $_2$ interface and roughly 12 times lower than the lowest previously reported coefficient for comparable nanowires.
Thermal Conductivity: The model-based film thermal conductivity ( $\kappa$ ) was estimated at $\approx 20$ mW/(m K).
Length Dependence: Across lengths of 1–50 $\mu$ m, $I_r$ does not follow pure longitudinal ( $\ell^{-1}$ ) or pure interfacial ( $\ell^0$ ) scaling. Instead, it transitions between these regimes. The data is well-described by a two-channel model with a crossover length $\ell^* \approx 3.5$ $\mu$ m (fitted values: 4.4–4.6 $\mu$ m), where contact cooling becomes significant for shorter wires.

Significance and Claims
The paper establishes that TiN films native to commercial CMOS processes can sustain self-heated hot spots, validating their potential for monolithic integration of superconducting nanowire detectors and logic with cryogenic readout electronics. The primary finding is that the electrothermal behavior is governed by vertical phonon-mediated cooling into the surrounding stack rather than longitudinal conduction to contacts for wires longer than a few micrometers.

The authors claim that the unusually low effective cooling coefficient ( $\Sigma_K$ ) explains both the low retrapping currents observed in long wires and the extended length scale over which contact cooling remains relevant. This weak vertical cooling, resulting from the complex series of interfaces and lack of a dedicated upper heat sink in the BEOL stack, distinguishes these buried films from surface-deposited nanowires. The work provides a quantitative framework (via $\Sigma_K$ and $\kappa$ ) for predicting the performance of such devices, enabling the design of superconductor-enhanced CMOS circuits without requiring custom fabrication processes.

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