⚛️ quantum physics

NeST: ultra-high-rate qLDPC codes with sub- $50\mu$ s stabiliser cycles via spin shuttling

This paper presents NeST, a co-designed architecture for silicon spin qubits that utilizes nested conveyor-belt shuttling tracks to implement ultra-high-rate qLDPC codes with sub-50μs stabilizer cycles, achieving fault-tolerant thresholds and logical error rates far superior to neutral-atom implementations while enabling efficient logical operations.

Original authors: Adam Siegel

Published 2026-10-21

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Adam Siegel

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

To build a computer that can solve problems beyond the reach of today's machines, scientists are turning to the strange rules of quantum physics. These machines use quantum bits, or qubits, which can exist in multiple states at once, allowing them to process vast amounts of information simultaneously. However, this power comes with a fragility: qubits are easily disturbed by their environment, causing errors that can ruin a calculation. To fix this, researchers use a method called quantum error correction, which spreads the information of a single logical bit across many physical qubits. If one physical bit fails, the others can cover for it, preserving the data. For years, the most popular way to do this has been the surface code, which arranges qubits in a flat grid where each one only talks to its immediate neighbors. While reliable, this method is incredibly inefficient, requiring thousands of physical qubits to create just one useful logical bit, making large-scale computers seem impossibly expensive.

A newer approach, known as quantum low-density parity-check codes, promises to change this math. These codes can encode information much more densely, potentially needing only a handful of physical qubits for every logical one. But they come with a catch: to work, they require qubits to interact with others that are far away, not just neighbors. This long-distance connection is difficult to build in solid-state hardware. Until now, the only platform capable of moving qubits around to make these distant connections work was a system using neutral atoms held in place by laser beams. These lasers can pick up and move atoms through empty space with great freedom, but they are slow and complex to control. A different type of hardware, silicon spin qubits, which are built using the same manufacturing processes as standard computer chips, offers a faster alternative. These qubits can be moved by shuttling electrons along tiny tracks, a process that happens in microseconds rather than milliseconds. The challenge has been that unlike atoms in free space, electrons on a chip must follow fixed paths and cannot crash into one another.

In this work, researchers have designed a new system that bridges this gap, creating the first complete plan that matches a high-performance quantum code with the specific capabilities of silicon spin qubits. They call this architecture NeST, which stands for Nested Shuttling Tracks. Instead of trying to force a complex code to fit onto a simple grid, they designed the hardware layout to naturally mimic the mathematical structure of the code itself. Imagine a factory floor where qubits are not static workers but trains moving on a series of nested conveyor belts. The system uses a flat square grid of tracks, but arranges them into loops within loops. Some loops carry the data qubits, which stay put, while others carry the helper qubits, which move along the tracks to perform calculations. The key innovation is that the movement of these helper qubits is not random; it is a rigid, synchronized motion where entire groups of qubits move together as a single unit, controlled by a global signal. This allows the system to perform the complex, long-range interactions required by the code without ever needing to stop and re-route individual qubits or risk a collision.

The researchers tested this design by simulating how well it would handle errors. They focused on a specific family of codes known as mitten codes, which are among the most efficient known, capable of encoding information at a rate of twenty percent. Their simulations showed that with this new architecture, the system could complete a full error-checking cycle in less than fifty microseconds. This is two to three times faster than previous methods using neutral atoms. Even more importantly, the simulations suggest that if the hardware can achieve a modest improvement in the reliability of moving the qubits, the system could reach a level of error protection where a logical qubit fails only once in every ten trillion rounds of calculation. This would require only nine physical qubits for every logical one, a massive reduction compared to the surface code, which would need over a thousand physical qubits to achieve the same level of safety.

The team also demonstrated that this architecture could handle the complex operations needed for actual computing, not just memory storage. To perform a calculation, a quantum computer must sometimes measure specific properties of the data, which involves temporarily attaching a special helper structure to the code. Usually, this process deforms the code in a way that breaks the neat, synchronized movement of the tracks. However, the researchers found a way to build this helper structure so that every qubit still moves only by rigid, global belt motions. They showed that for a specific, large version of their code, this could be done without adding any extra qubits and with only a small increase in the number of steps required for the calculation. This proves that the goals of ultra-low overhead and high speed are not mutually exclusive. By designing the code and the hardware together from the ground up, the researchers have shown that silicon spin qubits can provide both the speed and the efficiency needed to build a practical, large-scale quantum computer.

Technical Summary: NeST – Ultra-High-Rate qLDPC Codes with Sub-50µs Stabiliser Cycles via Spin Shuttling

Problem Statement
Quantum low-density parity-check (qLDPC) codes have recently achieved encoding rates up to 50% at useful distances, offering a significant reduction in physical qubit overhead compared to the surface code. However, these codes rely on long-range group actions rather than local nearest-neighbor interactions. While neutral-atom arrays can implement these codes by moving atoms through free space with optical tweezers, silicon spin qubits face a different constraint: electrons move along fabricated tracks where collisions are forbidden and permutations are fixed at the lithography stage rather than being dynamically reconfigurable. The central challenge addressed by this work is whether the "primitive" of coherent block transport exists for silicon spin qubits in a form capable of supporting the complex, non-abelian group actions required by ultra-high-rate qLDPC codes, and if so, how to design an architecture that routes these motions without collisions or excessive latency.

Methodology
The author proposes a co-design of the quantum error correction code and the silicon spin qubit hardware, termed NeST (Nested Shuttling Tracks).

Architectural Design:
- The architecture utilizes a plain square lattice of shuttling tracks.
- It implements a hierarchy of nested conveyor-belt loops. Data qubits remain static along these tracks, while ancilla qubits are shuttled collectively in "trains."
- The geometry mimics the structure of a family of non-abelian groups, $G(\vec{n}, \sigma)$ , defined as a product of cyclic groups with specific commutation relations (inversions).
- Group multiplications are mapped to rigid, globally controlled motions:
  - Cyclic shifts are achieved by rotating ancilla trains along a single loop.
  - Non-abelian inversions (e.g., $r \to r^{-1}$ ) are achieved by changing the direction in which an ancilla train enters a destination loop.
  - Higher-tier operations involve moving entire blocks of loops (cells) along inter-cell highways.
- This design ensures that every qubit moves synchronously without individual addressability, satisfying constraints for global control and collision avoidance.
Code Selection and Search:
- The author focuses on "mitten codes," a class of lifted product codes based on non-abelian groups.
- They conducted a deep code search within the implementable group family $G(\vec{n}, \sigma)$ to find codes with high rates and distances.
- They identified candidates up to $J_{1400, 280, \le 28K}$ , achieving a rate of 20%.
Simulation and Validation:
- Stabiliser circuits were compiled and mapped onto the NeST lattice, optimizing gate ordering to minimize circuit distance and shuttling overhead.
- End-to-end Monte-Carlo simulations were performed using the Stim simulator, incorporating a circuit-level depolarising noise model.
- The noise model included shuttling dephasing (proportional to distance), gate errors, and idling errors. Data qubit idling errors were mitigated via Hahn-echo techniques.
- A "code-surgery" gadget was constructed to demonstrate logical operations (measurement of logical Pauli operators) compatible with the rigid belt motion constraints.

Key Contributions

NeST Architecture: The first hardware architecture specifically designed to implement non-abelian group actions for qLDPC codes using silicon spin qubits. It translates abstract group multiplications into collision-free, rigid belt motions on a square lattice.
Code-Hardware Co-Design: The demonstration that the constraints of the hardware (fixed tracks, collision avoidance) can be satisfied by selecting specific group families, rather than forcing existing codes into a suboptimal routing scheme.
Logical Operations: The construction of a NeST-compatible code-surgery gadget. This gadget allows for the measurement of logical operators without breaking the rigid motion constraint, incurring no additional qubit overhead and only a 29% increase in gate layers.
Performance Benchmarks:
- Speed: Stabiliser cycles are achieved in sub-50µs (e.g., 16.4µs for the $J_{150, 30, 10K}$ code), which is two to three orders of magnitude faster than neutral-atom implementations.
- Thresholds: Circuit-level simulations show error thresholds above $10^{-3}$ even with significant shuttling dephasing.
- Overhead: For a target logical error rate of $10^{-14}$ at a physical error rate of $p=0.1\%$ , the author estimates that a distance-27 mitten code would require only 9 physical qubits per logical qubit, compared to 1,457 for a surface code, assuming a ten-fold improvement in shuttling fidelities over early demonstrations.

Results

Thresholds: The simulated codes maintain thresholds above $p=0.1\%$ (a common target for utility-scale machines) across various shuttling dephasing assumptions, including cases where dephasing is $p/20$ per micrometer.
Scaling: The logical error rate scales favorably with code distance. The author estimates that the $J_{1400, 280, \le 28K}$ code could reach a logical error probability of $10^{-14}$ per round, contingent on a ten-fold improvement in shuttling fidelities over current early demonstrations.
Efficiency: The architecture successfully routes the complex permutations required by mitten codes without the routing depth penalties seen in previous code-agnostic approaches.

Significance and Claims
The paper claims to demonstrate that ultra-low-overhead fault tolerance and fast clock speeds are not competing goals in the context of silicon spin qubits. By leveraging electron shuttling to implement non-abelian group actions, NeST enables the use of high-rate qLDPC codes that were previously thought to require the free-space mobility of neutral atoms. The work establishes that silicon spin qubits can supply both the necessary connectivity for these codes and the speed required for practical quantum computation, provided that shuttling fidelities continue to improve. The author emphasizes that their architecture relies on primitives (conveyor-mode shuttling, junctions) that have already been experimentally demonstrated, positioning the NeST design as a feasible near-term path forward for silicon-based quantum error correction.

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