⚡ electrical engineering

Fabrication-aware inverse-designed Y-junctions for multiple asymmetric splitting ratios: trade-off between bandwidth, excess loss, and tolerance

This paper presents a fabrication-aware inverse design method for robust Y-junctions that achieves multiple asymmetric splitting ratios with low loss, broadband operation, and high tolerance to process variations, thereby enhancing the manufacturability and performance of integrated photonic circuits.

Original authors: Minghao Jiang, Junbo Yang, Xin He

Published 2026-08-11

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CC BY 4.0

Original authors: Minghao Jiang, Junbo Yang, Xin He

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine a world where computers don't just use electricity to think, but light. This is the realm of photonics, a field that promises to make our devices faster, cooler, and more powerful by sending information on beams of light instead of electrons. But for light to do its job inside a tiny computer chip, it needs a road system. Just like a highway needs exits and on-ramps, a light-based chip needs devices to split a single beam of light into two, three, or more paths. One of the most important tools for this job is called a Y-junction. You can picture it as a fork in the road for light, where one stream splits into two.

However, building these microscopic light-forks is incredibly tricky. In the real world, manufacturing isn't perfect. Machines can be slightly off, etching too deep or not deep enough, or making a line a tiny bit wider or narrower than intended. These tiny "glitches" are like potholes on a highway; if the road isn't built perfectly, the light might crash, scatter, or take the wrong turn, ruining the signal. For a long time, scientists designed these light-forks using old-school methods that assumed everything would be built perfectly. But when they actually built them, the performance often crashed. The big question has been: How do we design a light-fork that is so smart and sturdy that it keeps working perfectly, even if the factory makes a few tiny mistakes?

This paper tackles that exact problem by introducing a new way to design these Y-junctions using a technique called inverse design. Instead of guessing shapes and testing them one by one, the researchers used powerful computer algorithms to work backward from the perfect result to find the best shape. But here is the twist: they didn't just ask the computer to find the "perfect" shape for a perfect factory. They told the computer, "Imagine the factory makes mistakes. Now, find a shape that still works even if the silicon layer is 20 nanometers thinner than planned, or if the gap between the branches is slightly off."

The researchers simulated a standard silicon chip environment where the top layer of silicon is 220 nanometers thick. They discovered that while their designs were very forgiving of width errors (being a bit too wide or too narrow) and gap errors, they were very sensitive to the thickness of the silicon layer. Specifically, if the silicon was etched too deep (making it 20 nanometers thinner), the light got lost. To fix this, they developed a "robust optimization" strategy. They didn't just design for the ideal case; they designed for the worst-case scenario of a thin silicon layer, balancing the need for a perfect split with the need for durability.

The result is a family of Y-junctions that can split light into different ratios, not just the usual 50/50 split. The team successfully simulated designs that split light in ratios of 4:6, 3:7, and even 2:8. In these simulations, the devices showed excellent performance. For the 4:6 split, the total light transmission was 0.803, with a splitting ratio of 3.96:6.04. Even for the more extreme 2:8 split, the device worked, though the total transmission dropped to 0.615 as the design had to bend the light more sharply to achieve that imbalance.

Crucially, the paper shows that these designs are not just theoretical fantasies; they are built to survive the messy reality of manufacturing. The simulations indicate that even with the tricky thickness errors, the devices maintain low insertion loss (meaning very little light is wasted) and stay stable. The researchers found that by making small, smooth adjustments to the curves of the light path—rather than creating wild, complex shapes—they could achieve these flexible splits without making the device too hard to build. This work suggests that we can now create light-splitters that are not only compact and efficient but also tough enough to handle the inevitable imperfections of real-world factories, paving the way for more reliable optical computers and communication systems.

Problem Statement

Y-junctions are fundamental passive components in photonic integrated circuits (PICs), essential for on-chip optical power splitting, combining, and routing. While they offer advantages such as broadband operation, low reflection, and ease of cascading, their practical deployment is hindered by sensitivity to fabrication errors. Conventional inverse-designed devices often rely on delicate local geometric controls that, when subjected to process variations (e.g., over-etching, under-etching, sidewall roughness, or tip rounding), suffer from mode mismatch, scattering loss, and splitting-ratio deviations.

Existing design methods struggle to simultaneously achieve compact size, multiple asymmetric splitting ratios, and high fabrication robustness. Furthermore, while inverse design has advanced device performance, many approaches lack explicit consideration for manufacturability and process variations, leading to performance degradation in real-world cascaded systems where errors accumulate.

Methodology

The authors propose a fabrication-oriented robust optimization framework for designing Y-junction splitters on a standard Silicon-on-Insulator (SOI) platform (220 nm silicon core, 3 µm buried oxide). The methodology employs a phased optimization approach combining shape-adaptive optimization, curved waveguide optimization, and Direct Binary Search (DBS) algorithms.

1. Phased Optimization Strategy:

Stage 1 (Shape Optimization): The Y-junction coupling region is optimized using a shape-adaptive algorithm to maximize electric field intensity at the target, minimizing insertion loss between the input and output waveguides.
Stage 2 (Curved Waveguide Optimization): The curved branch regions are further optimized to minimize scattering and mode loss caused by bending, ensuring smooth field transition.

2. Robustness Optimization:
Recognizing that silicon thickness deviation is the dominant sensitive factor (specifically negative deviations), the authors introduce a local robust re-optimization strategy around the nominal optimum. Instead of a global re-design, they release specific spline control points while fixing others. Two robust objective functions are defined to balance nominal performance with tolerance to fabrication corners:

Scheme 1: Weights the nominal response ( $J_{nom}$ ) and the response under a -20 nm thickness deviation ( $J_{h-20}$ ).
Scheme 2: Adds an intermediate -10 nm deviation ( $J_{h-10}$ ) to the objective function to ensure smoother performance across a range of negative thickness biases.

3. Asymmetric Splitting Ratio Control:
To achieve multiple asymmetric splitting ratios (4:6, 3:7, 2:8) without redesigning the entire topology or introducing complex digital pixels, the authors apply local boundary perturbations to the second-stage branching bend region of the high-transmission symmetric Y-branch.

Smooth, constrained geometric offsets are applied to the upper and lower branch boundaries using an envelope function that peaks in the bending region and tapers near the ports to avoid sharp corners.
The optimization minimizes a cost function ( $L$ ) comprising splitting-ratio error, total transmission loss, and a geometric penalty term ( $P_g$ ) to ensure manufacturability.

Key Contributions

Fabrication-Aware Robust Design: Explicitly incorporates process variation models (specifically negative silicon thickness bias) into the inverse design objective function, moving beyond nominal-only optimization to improve repeatability under practical fabrication conditions.
Unified Multi-Ratio Framework: Demonstrates a unified design approach that supports multiple asymmetric splitting ratios (4:6, 3:7, 2:8) by perturbing a single robust symmetric base structure, avoiding the need for distinct topologies for each ratio.
Low-Complexity Tuning: Proposes a method that preserves the continuity and manufacturability of the initial design by avoiding subwavelength discrete features, contrasting with pixelated inverse design or deep learning methods that require extensive training data or complex fabrication.

Results

1. Fundamental Optical Characteristics:
The optimized Y-branch exhibits broadband low-loss operation across the 1200–2000 nm wavelength range.

Transmission: Remains above 0.9, peaking at ~0.9912 near the central wavelength.
Insertion Loss: Ranges from 0.0385 to 0.4504 dB, staying below 0.2 dB for most of the 1200–1900 nm range.

2. Robustness and Tolerance Analysis:

Width and Gap Errors: The device shows good tolerance to ±20 nm width and gap deviations, with insertion loss remaining below 0.2 dB in the 1200–1900 nm range.
Thickness Errors: Negative thickness deviation (-20 nm) is identified as the critical factor, significantly increasing the maximum insertion loss to ~0.7444 dB compared to width and gap errors. The robust optimization strategy aims to mitigate this sensitivity relative to a nominal-only design by explicitly weighting the -20 nm corner in the objective function, though the paper notes that thickness deviation remains the most significant process-sensitive factor affecting performance.

3. Asymmetric Splitting Ratios:
The local boundary perturbation method successfully achieved the target ratios with high accuracy:

4:6 Split: Achieved ratio 3.96:6.04; Total transmission ( $T_{total}$ ) = 0.803; Geometric penalty ( $P_g$ ) = 0.00335.
3:7 Split: Achieved ratio 3.03:6.97; $T_{total}$ = 0.704; $P_g$ = 0.00608.
2:8 Split: Achieved ratio 1.96:8.04; $T_{total}$ = 0.615; $P_g$ = 0.014.

The results indicate a trade-off: as the splitting ratio becomes more asymmetric, total transmission decreases and geometric deformation increases, but the method remains effective for moderate to strong asymmetry.

Significance and Claims

The paper claims to provide a practical reference for designing high-performance, scalable, and manufacturable integrated photonic devices. By addressing the trade-off between bandwidth, excess loss, and fabrication tolerance, the work aims to advance the engineering application of Y-junctions in:

Optical Computing: Providing flexible power distribution for neuromorphic photonic computing.
Optical Interconnects: Enabling low-loss, broadband signal routing.
Integrated Photonic Systems: Supporting complex optical networks, on-chip power monitoring, and feedback control loops.

The authors emphasize that their approach improves the practical feasibility of inverse-designed devices by explicitly accounting for manufacturing constraints, thereby reducing the performance gap between simulation and fabricated reality.

Problem Statement

Methodology

Key Contributions

Results

Significance and Claims

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