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Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

This paper introduces StructRTL, a novel structure-aware graph self-supervised learning framework that leverages control data flow graphs and knowledge distillation from post-mapping netlists to significantly outperform existing LLM-based methods in estimating RTL design quality metrics like area and delay.

Original authors: Yi Liu, Hongji Zhang, Yiwen Wang, Dimitris Tsaras, Lei Chen, Mingxuan Yuan, Qiang Xu

Published 2026-06-01

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Yi Liu, Hongji Zhang, Yiwen Wang, Dimitris Tsaras, Lei Chen, Mingxuan Yuan, Qiang Xu

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are an architect designing a massive, intricate skyscraper. Before you even pour the concrete or lay the bricks, you want to know: Will this building be too heavy? Will the elevators be too slow?

In the world of computer chip design, this is exactly what engineers face. They write code (called RTL) to describe how a chip should work. To find out if the chip will be fast enough or small enough, they usually have to run a massive, slow computer simulation called "logic synthesis." It's like building a full-scale model of the skyscraper just to measure it. This takes a long time and slows down the whole design process.

The paper you provided introduces a new tool called StructRTL. Think of it as a "super-quick crystal ball" that can look at the blueprints (the code) and instantly guess the building's weight and speed, without needing to build the model first.

Here is how it works, broken down into simple concepts:

1. The Problem: Reading the "Wrong" Book

Previous attempts to build this "crystal ball" used two main methods, both of which had flaws:

The "Token" Method (LLMs): This is like asking a smart robot to read the blueprint line-by-line, word by word. While the robot is great at understanding grammar and vocabulary, it often misses the big picture of how the rooms connect. It sees the words "door" and "hallway" but doesn't fully grasp the complex structural flow between them.
The "Hand-Crafted" Method: This is like asking a human to count the number of windows and doors and plug those numbers into a simple calculator. It's too rigid and misses the subtle, complex relationships in the design.

2. The Solution: The "Structural Map" (CDFG)

The authors realized that to predict how a chip will perform, you need to see its skeleton, not just its text. They use a special map called a Control Data Flow Graph (CDFG).

The Analogy: Imagine taking the blueprint and turning it into a subway map.
- Nodes (Stations): These are the operations (like adding numbers) or storage (like memory registers).
- Edges (Tracks): These show how data flows from one station to another.
- The Difference: Unlike a text document, this map explicitly shows how the pieces are connected. It reveals the "traffic jams" (delays) and the "construction costs" (area) hidden in the code.

3. How StructRTL Learns: The "Fill-in-the-Blanks" Game

Instead of just memorizing the map, StructRTL teaches itself by playing a game called Self-Supervised Learning. It's like a teacher hiding parts of a subway map and asking the student to guess what's missing.

Task 1: Guess the Station Type (Masked Node Modeling): The computer covers up a station on the map and asks, "Is this a 'Train Station' (an adder) or a 'Bus Stop' (a memory register)?" To guess correctly, the AI has to understand the context of the surrounding tracks. This teaches it what each part does.
Task 2: Guess the Tracks (Edge Prediction): The computer hides the lines connecting the stations and asks, "Does a track go from Station A to Station B?" This forces the AI to understand the structure and flow of the design.

By playing these games millions of times on thousands of designs, the AI learns to "feel" the structure of a chip. It learns that certain patterns of connections usually mean the chip will be slow, while others mean it will be small.

4. The Secret Sauce: "Teacher-Student" Coaching

Even with a great map, predicting the final weight and speed is hard because the map is an abstract sketch, not the finished building. To get even better, StructRTL uses a Knowledge Distillation strategy.

The Analogy: Imagine a Master Builder (the "Teacher") who has already built the skyscraper and knows its exact weight and speed.
The Process: The Master Builder looks at the finished building and explains the details to the Student (StructRTL). The Student tries to mimic the Master's understanding.
The Result: The Student learns the "low-level secrets" of the finished building and applies them to the blueprints. This allows the Student to make incredibly accurate predictions just by looking at the map, without needing to build the whole thing.

5. The Results: Fast and Accurate

The paper claims that this new method is a huge improvement:

Speed: It predicts chip quality in a fraction of a second (about 0.1 seconds), whereas the traditional method takes about 14 seconds. That's a 145x speedup.
Accuracy: It is much better at guessing both the size (area) and the speed (delay) of the chip than previous methods, including those using giant AI language models.
Small Data: It works well even if you don't have a massive amount of training data, which is great for new chip technologies where data is scarce.

Summary

StructRTL is a new way to predict how good a computer chip design will be. Instead of reading the code like a story or counting parts like a spreadsheet, it turns the code into a structural map and trains an AI to understand the connections on that map. By teaching the AI to fill in missing parts of the map and letting it learn from a "Master Builder" who has already built the chips, it can instantly tell engineers if their design will be fast and efficient, saving them hours of waiting time.

Technical Summary: Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

Problem Statement

In the Electronic Design Automation (EDA) workflow, estimating the quality of Register Transfer Level (RTL) designs—specifically metrics like area and delay—is critical for providing instant feedback without the computational expense of full logic synthesis. While recent approaches have leveraged Large Language Models (LLMs) to derive embeddings from RTL code tokens, the authors argue these methods overlook essential structural semantics. Token-based views encode structural information implicitly, whereas Control Data Flow Graphs (CDFGs) explicitly expose the design's structural characteristics, offering richer cues for representation learning. Furthermore, existing graph-based methods often rely on shallow, hand-crafted features that fail to capture the complex patterns affecting downstream performance.

Methodology

The paper introduces StructRTL, a structure-aware graph self-supervised learning framework designed to improve RTL design quality estimation. The methodology consists of four main components:

1. CDFG Construction

Instead of processing raw RTL code tokens, StructRTL operates on Control Data Flow Graphs (CDFGs). The construction pipeline involves:

Compiling RTL source code into RTL Intermediate Language (RTLIL) using Yosys.
Generating an Abstract Syntax Tree (AST) from RTLIL using the Stagira Verilog parser.
Traversing the AST to extract the CDFG, where nodes represent operations or storage elements, and directed edges indicate data or control dependencies.

2. Model Architecture

StructRTL employs a hybrid architecture combining a Graph Neural Network (GNN) and a Transformer encoder:

Initialization: Node embeddings are initialized by concatenating the one-hot encoding of the node type and the node width.
GNN Processing: A Graph Isomorphism Network (GIN) performs message passing to generate context-aware embeddings.
Positional Encoding: To preserve structural information lost when flattening the graph for the Transformer, global positional embeddings are computed using the eigenvectors of the symmetric normalized Laplacian matrix of the directed graph.
Transformer Encoder: The context-aware embeddings, combined with positional embeddings, are processed by a Transformer encoder to produce final structure-informed embeddings.

3. Self-Supervised Pretraining

To learn rich representations, the model undergoes two tailored pretraining tasks on the CDFGs:

Structure-Aware Masked Node Modeling: Unlike standard masking of raw features, this task masks post-GNN context-aware embeddings. The model predicts the original node type (a 32-class classification problem) for masked nodes. To address severe class imbalance (e.g., rare operators vs. common wires), the authors employ stratified masking (ensuring minimum samples per class) and class-balanced focal loss.
Edge Prediction: Since flattening the graph for the Transformer obscures connectivity, this task treats edge recovery as a binary classification problem. The model predicts whether an edge exists between two nodes based on their final embeddings, using a Multi-Layer Perceptron (MLP).

4. Knowledge Distillation

To bridge the gap between RTL-level CDFGs and the actual post-mapping (PM) netlists where area and delay are measured, the authors incorporate a knowledge distillation strategy:

A PM-based predictor is first trained on synthesized netlists (using a GIN) and frozen.
This predictor guides the CDFG-based predictor (StructRTL) by aligning their final-layer activations via a loss function combining cosine similarity and mean squared error. This transfers low-level insights from the gate-level view to the RTL-level model.

Key Contributions

StructRTL Framework: A novel self-supervised learning framework that explicitly leverages CDFGs rather than token sequences to capture structural semantics.
Tailored Pretraining Tasks: The introduction of structure-aware masked node modeling and edge prediction specifically adapted for computational graphs, addressing the ambiguity issues inherent in masking raw CDFG nodes.
Cross-Stage Supervision: The integration of knowledge distillation from post-mapping netlists to enhance the predictive accuracy of RTL-level estimators.
Open Source: The code is released to facilitate further research.

Experimental Results

The authors evaluated StructRTL on a dataset of 13,200 designs, comparing it against graph-based baselines (Graph-XGBoost, Graph-GNN) and LLM-based baselines (CodeV variants).

Performance: Without knowledge distillation, StructRTL achieved an $R^2$ score of 0.7463 for area prediction and 0.7630 for delay prediction, significantly outperforming the previous state-of-the-art LLM-based methods (which scored ~0.63 and ~0.52 respectively).
With Knowledge Distillation: When incorporating the distillation strategy, StructRTL further improved to 0.8676 ( $R^2$ ) for area and 0.8872 for delay, surpassing all baselines.
Ablation Studies: Removing either pretraining task (masked node modeling or edge prediction) resulted in performance degradation, confirming the necessity of both tasks.
Data Efficiency: StructRTL maintained competitive performance even when trained on only 20% of the data, outperforming full-data LLM baselines.
Industrial Evaluation: On 102 industrial RTL modules, StructRTL achieved 82.35% accuracy in area ranking and 88.23% in delay ranking for pairwise comparisons.
Inference Speed: StructRTL provides near-instantaneous feedback, averaging 0.096 seconds per design compared to 13.97 seconds for logic synthesis (a 145× speedup).

Significance and Claims

The paper claims that combining structural representation learning with cross-stage supervision establishes new state-of-the-art results in RTL quality estimation. The authors emphasize that the explicit encoding of structural semantics in CDFGs, coupled with self-supervised learning and knowledge distillation, allows the model to capture complex design patterns that token-based LLMs miss. This approach offers a practical solution for accelerating design cycles by enabling accurate, early-stage quality feedback without the computational burden of full synthesis, while remaining computationally efficient enough for iterative design workflows. The work highlights that while LLMs excel at code generation, they may lack the explicit structural inductive bias required for precise hardware quality estimation, a gap that structural graph learning effectively fills.