Robust Synchronous Reference Frame Phase-Looked Loop (PLL) with Feed-Forward Frequency Estimation

Technical Summary: Robust Synchronous Reference Frame Phase-Locked Loop with Feed-Forward Frequency Estimation

Problem Statement
Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) techniques are standard for synchronization and control in power systems and energy conversion. However, conventional SRF-PLLs, which typically rely on a Proportional-Integral (PI) feedback loop with two integrators, face limitations in dynamic environments. Specifically, while Type-2 PLLs can eliminate steady-state errors for step frequency changes, they exhibit non-zero steady-state errors when tracking frequency ramps—a common scenario in servo-systems like motor drives. Increasing loop gains to compensate for these errors reduces phase margin and increases noise sensitivity. Furthermore, higher-order PLLs (e.g., Type-3) that theoretically eliminate ramp errors often compromise robustness and stability. Additionally, conventional designs are sensitive to input amplitude variations and measurement noise, often requiring complex observers or additional filtering loops that introduce modeling errors or tuning burdens.

Methodology
The authors propose a novel SRF-PLL architecture (denoted SRF-PLL-FF) that enhances the conventional structure with a robust, model-free feed-forward frequency estimator. The methodology comprises three main components:

1. Power-Invariant Normalization: To decouple the loop gain from input amplitude variations, the authors introduce a normalization scheme based on the power-invariant property of the abc-dq transformation. Instead of using the $Z_d$ component (which requires low-pass filtering and introduces phase lag), the input three-phase signals are normalized by the rotary vector magnitude $N(Z_{\{a,b,c\}}) = \sqrt{Z_a^2 + Z_b^2 + Z_c^2}$. This ensures the normalized signal magnitude remains constant regardless of input amplitude fluctuations.
2. Symmetrical Optimum Feedback Design: The PI controller gains ($k_p, k_i$) for the feedback loop are tuned using the symmetrical optimum method to maximize the phase margin at the crossover frequency, accounting for inherent sampling delays.
3. Robust Feed-Forward Estimator: A model-free, second-order frequency estimator (based on prior work [18]) is employed to generate the feed-forward signal. This estimator operates directly on the measured three-phase signals without requiring a dynamic system model or additional observers. It utilizes an adaptation law with a single tunable gain parameter ($\gamma$). To enhance robustness against noise and temporary data loss, three identical estimators run in parallel for each phase ($a, b, c$), and their outputs are averaged to produce the final feed-forward frequency estimate ($\tilde{\omega}$).

Key Contributions

• Model-Free Robustness: The proposed feed-forward estimator is model-free and operates directly on measured harmonic signals, making it suitable for noisy and time-varying environments without the need for system identification.
• Ramp Tracking without Order Increase: By injecting the estimated frequency into the loop, the equivalent input becomes a step signal rather than a ramp. This allows the system to track frequency ramps with zero steady-state error without increasing the loop order (maintaining the standard two integrators), thereby preserving the robustness and phase margin of the conventional design.
• Amplitude Independence: The power-invariant normalization scheme renders the PLL loop transfer characteristics insensitive to input amplitude variations, simplifying tuning and improving stability.
• Real-Time Executability: The implementation requires only standard integrators and scalar algebraic expressions, avoiding extensive pre- or post-processing, making it suitable for real-time execution on standard control platforms.

Experimental Results
The proposed SRF-PLL-FF was experimentally evaluated on a 3-phase PMSM drive system using a voltage source inverter (8 kHz switching frequency) and a dSPACE 1006 control platform. The evaluation compared the proposed scheme against a standard SRF-PLL (with feed-forward set to zero) under two conditions:

1. Torque-Varying Operation: Experiments at 50 rad/s and 150 rad/s with stepwise load changes. The SRF-PLL-FF demonstrated superior performance in maintaining synchronization during transient peaks and recovered quickly from temporary data loss (approx. 0.05 s).
2. Frequency Ramp Operation: A controlled ramp start-up sequence typical of motor acceleration. The SRF-PLL-FF achieved significantly faster phase locking and reduced synchronization error compared to the standard PLL.

Quantitative error metrics (accumulative absolute error and absolute mean error) showed a consistent reduction in phase synchronization error for the SRF-PLL-FF. For instance, during the frequency ramp operation, the absolute mean error dropped from 0.9205 (standard PLL) to 0.1327 (SRF-PLL-FF). Similarly, waveform reconstruction Root Mean Square Error (RMSE) was significantly lower for the proposed method, particularly during ramp operations (0.0513 vs. 0.2909).

Significance and Claims
The paper claims that the proposed SRF-PLL-FF offers a considerable improvement over standard SRF-PLL techniques widely used in motor drives and power electronics. The significance lies in achieving robust frequency and phase locking under dynamic conditions (load transients and frequency ramps) and in the presence of measurement noise, all without increasing the loop order or hardware costs. The authors emphasize that the approach maintains the simplicity and industrial viability of the standard two-integrator PLL while overcoming its primary limitation in tracking frequency ramps. The method is presented as a practical, real-time executable solution that requires only one additional tuning parameter for the estimator, alongside the standard PI tuning.