Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

Technical Summary: Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

Problem Statement
The proliferation of Spiking Neural Networks (SNNs) has driven the development of neuromorphic architectures capable of mimicking biological spike-based processing. While SNNs offer significant advantages in energy efficiency and parallel computing, their widespread adoption is hindered by the prohibitive costs of silicon tape-outs. Furthermore, existing neuromorphic hardware often lacks accessibility for open-source design and flexible prototyping. A critical architectural challenge is the control of standalone SNN accelerators; solutions relying on external controllers are often suboptimal regarding energy efficiency, which is paramount for edge applications. There is a need for a flexible, cost-effective platform that integrates a local controller with an SNN accelerator to facilitate open-source hardware development and edge deployment without the expense of custom silicon.

Methodology
The authors present a heterogeneous System-on-Chip (SoC) design implemented on FPGAs that integrates ReckOn, an open-source Recurrent SNN (RSNN) accelerator, with two distinct control architectures. The ReckOn accelerator supports up to 256 input/recurrent Leaky Integrate-and-Fire (LIF) neurons and 16 output Leaky Integrate (LI) neurons, utilizing the e-prop algorithm for local in-space and time learning.

Two heterogeneous configurations were synthesized on a Xilinx Zynq-7020 (XC7Z020) FPGA (PYNQ-Z2 board):

1. X-HEEP Microcontroller Integration:

   • Controller: An open-source RISC-V-based microcontroller (X-HEEP) synthesized as a standalone digital system.
   • Interface: The X-HEEP controls the ReckOn accelerator via an SPI peripheral.
   • Data Handling: Training and test datasets are stored in Block RAM (BRAM) and initialized during bitfile writing. An Address Event Representation (AER) decoder, implemented as a Finite State Machine (FSM), decodes 32-bit words from memory into spike events and manages the handshake with the accelerator.
   • Operation: The system operates in a "bare metal" environment, managing the configuration of the parameter bank and the execution of inference/training cycles.

2. ARM Processor Integration (Zynq SoC):

   • Controller: The ARM Cortex-A9 Processing System (PS) running a Linux-based OS (PetaLinux).
   • Interface: The PS controls the ReckOn accelerator (implemented in the Programmable Logic, PL) via memory-mapped AXI interfaces (AXI-QUADSPI, AXI-BRAM, AXI-GPIO).
   • Data Handling: To overcome BRAM capacity limitations, this architecture employs a batch-offloading mechanism. Datasets are stored in the PS memory and transferred in batches to the PL BRAM.
   • Operation: The AER decoder was modified to support batch processing, introducing new FSM states (e.g., END_B, NEW_BATCH) and signals to coordinate with the ARM controller. This allows for the execution of larger tasks and more complex datasets.

Key Contributions

• Heterogeneous Integration: The successful integration of the ReckOn RSNN accelerator with both a RISC-V-based microcontroller (X-HEEP) and a commercial ARM-based SoC, demonstrating a flexible ecosystem for neuromorphic edge computing.
• Open-Source Validation: The work validates the ReckOn accelerator on FPGA, confirming its equivalence to the original silicon tape-out implementation.
• Scalable Architecture: The development of an ARM-controlled architecture that utilizes batch offloading to handle datasets larger than the FPGA's on-chip memory, addressing a key limitation of the microcontroller-only approach.
• Online Learning Demonstration: The implementation and evaluation of online learning capabilities using the e-prop algorithm on a real-world dataset (Braille digits) directly on the FPGA.

Results
The authors validated the designs through resource utilization analysis and accuracy benchmarks:

• Resource Utilization:
  • The X-HEEP implementation utilized approximately 91.1% of available LUTs and 71.07% of BRAMs (due to dataset storage), leaving limited room for additional IPs.
  • The ARM-based implementation utilized 77.7% of LUTs and 86.07% of BRAMs. By offloading the controller to the PS, this design freed up resources and allowed for more flexible configuration.
• Accuracy Validation (Binary Decision Navigation):
  • The FPGA implementations were compared against the original silicon tape-out results and RTL simulations using the Cue Accumulation dataset.
  • X-HEEP: Achieved 92.4% training and 96.8% validation accuracy.
  • ARM: Achieved 92.2% training and 96.4% validation accuracy.
  • Silicon Reference: Reported 96.4% accuracy.
  • The results confirm no significant discrepancy between the FPGA implementations and the silicon tape-out.
• Online Learning (Braille Digits Classification):
  • The system was tested on a subset of the Braille digits dataset (12 input sensors).
  • 3-Class Subset (A, E, U): Achieved 90% accuracy on the test set after 200 epochs.
  • 4-Class Subsets: Achieved 78.8% accuracy for classes {A, E, U, Space} and 60% for {A, E, O, U}.

Significance
The paper claims that targeting FPGAs offers a viable, cost-effective alternative to silicon tape-outs for developing and spreading open-source neuromorphic hardware designs. By integrating the accelerator with traditional processors (both RISC-V and ARM), the authors demonstrate a practical pathway for edge computing applications that require local control for energy efficiency. The work validates that FPGA-based implementations can match the accuracy of silicon counterparts while offering the flexibility to run online learning tasks on diverse datasets, such as Braille digit recognition, without the need for custom chip fabrication. The authors note that future work will involve a full comparison with state-of-the-art neuromorphic hardware evaluated in the Neuromorphic Intermediate Representation (NIR) framework.