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Silicon Photonics Testing: Design for Testability, Fault Detection, and Manufacturing Variation Analysis in Photonic Integrated Circuits

This paper proposes and validates a design-for-test (DFT) methodology and architecture for silicon photonic integrated circuits, demonstrating its effectiveness in detecting faults and verifying signal power and phase across diverse applications including optical neural networks and logic circuits with feedback loops.

Original authors: Pratishtha Agnihotri, Priyank Kalla, Steve Blair

Published 2026-06-09

📖 5 min read🧠 Deep dive

CC0 1.0

Original authors: Pratishtha Agnihotri, Priyank Kalla, Steve Blair

Original paper dedicated to the public domain under CC0 1.0 (http://creativecommons.org/publicdomain/zero/1.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are building a massive, incredibly complex city out of glass pipes. In this city, instead of cars, light travels through the pipes to carry information. This is the world of Silicon Photonics. It's a super-fast, high-tech way to move data, but there's a catch: because the pipes are so tiny (smaller than a human hair), even a microscopic speck of dust or a tiny error in how they were cut can ruin the whole system. If the pipes are slightly the wrong width, the light might get lost, arrive at the wrong time, or crash into other light beams in a messy way.

The paper you provided is about building a specialized "inspection team" directly inside these glass cities to catch these mistakes before the city is finished.

Here is a breakdown of their solution using simple analogies:

1. The Problem: The "Ghost" in the Machine

In traditional electronics (like the chips in your phone), we have well-known ways to test if a circuit works. But in these light-based chips, it's hard to peek inside without breaking the flow.

The Issue: If a pipe is built slightly too wide or too narrow during manufacturing, the light signal changes. It might get dimmer (power loss) or arrive a split-second too late (phase shift).
The Consequence: The chip might think "1" when it should think "0," or the data might just disappear. Currently, fixing this is like trying to tune a radio by guessing; it's slow, manual, and expensive.

2. The Solution: The "Taste-Tester" Architecture

The authors propose a Design-for-Test (DFT) method. Think of this as installing a built-in "taste-tester" station right inside the factory line of the chip.

Instead of just letting the light flow from Point A to Point B, they insert a special device that acts like a traffic cop and a mirror at the same time.

The Key Component: The Mach-Zehnder Modulator (The "Splitter")

Imagine a river (the light signal) flowing down a channel. The authors put a special dam in the middle called a Mach-Zehnder Modulator (MZM).

Normal Mode: When the chip is working normally, the dam is open, and the river flows straight through to the next part of the city.
Test Mode: When it's time to check for errors, the dam is adjusted to tap off a small sample of the water (30% of the light) and send it to a side channel for inspection. The rest of the water keeps flowing so the chip can keep working.

The Comparison: The "Y-Combiner" (The "Cancel-Out" Machine)

Once the sample of light is tapped off, it needs to be checked. How do we know if it's "wrong"?

The authors create a perfect, ideal version of what the light should look like. Let's call this the "Reference Signal."
They take the Sample Signal (from the chip) and the Reference Signal (the perfect ideal) and smash them together into a Y-shaped pipe (a Y-combiner).
The Magic Trick: They set it up so that if the two signals are perfectly identical, they cancel each other out completely (like noise-canceling headphones). The result is silence (no light).
- Silence = Good: The chip is perfect.
- Light = Bad: If you see light coming out of the Y-pipe, it means the Sample Signal didn't match the Reference Signal. There is a defect!

3. Putting It to the Test

The authors tested this "inspection team" on two very different types of light-cities:

Case A: The Optical Neural Network (The "Brain")
- This is a chip designed to think like a human brain, using layers of light pipes.
- They replaced one of the standard light-switches in the brain with their "inspection station."
- Result: When they simulated a defect (a pipe that was slightly bent), the inspection station caught it immediately because the light didn't cancel out perfectly.
Case B: The Optical Logic Circuit with Loops (The "Roundabout")
- This is a chip where the light pipes loop back on themselves, like a roundabout. This is trickier because the light keeps circling.
- They couldn't just replace a part inside the loop, so they inserted their inspection station between two parts of the loop.
- Result: Even with the light circling around, the station successfully detected when a part of the loop was broken.

Summary

In short, this paper says: "Don't wait until the chip is finished to see if it works. Build a built-in 'quality control' station that taps off a little bit of light, compares it to a perfect ideal, and tells you instantly if there's a mistake."

They proved this works by simulating the whole process on a computer, designing the tiny glass pipes, and showing that their "cancel-out" method can spot even tiny manufacturing errors in complex light-based computers. This could help make these high-tech chips cheaper and more reliable in the future.

Technical Summary: Silicon Photonics Testing: Design for Testability, Fault Detection, and Manufacturing Variation Analysis in Photonic Integrated Circuits

Problem Statement
The rapid expansion of silicon photonics into high-bandwidth, cost-effective interconnects and complex systems like optical neural networks (ONNs) and optical logic circuits has been driven by the high refractive index contrast of silicon-on-insulator (SOI) and compatibility with CMOS processes. However, this technology faces significant challenges regarding manufacturing yield and reliability. Silicon photonic circuits are highly sensitive to minor geometric discrepancies (e.g., waveguide width or thickness variations) inherent in fabrication. These deviations propagate through complex circuits, altering signal power and phase, causing faulty interference patterns, and ultimately leading to performance deterioration. While post-fabrication tuning and calibration are necessary, current processes are largely manual, tedious, and lack automation. Furthermore, there is a distinct gap in research regarding automated Design-for-Test (DFT) architectures specifically designed to simplify testing, diagnosis, and calibration of Photonic Integrated Circuits (PICs).

Methodology
The authors propose a specification-based DFT architecture designed to be embedded directly into silicon PICs. The core methodology involves:

Test Access and Signal Tapping: Utilizing a Mach-Zehnder Modulator (MZM) based on carrier injection to tap a portion of the optical signal at specific test points. The MZM is designed to operate in an "intermediate configuration" (test mode) where a specific percentage (30%) of the signal is diverted for testing while the remainder continues through the circuit.
Fault Detection via Comparison: The tapped test signal (amplitude $S_T$ , phase $\phi_T$ ) is compared against a known reference signal ( $S_R$ , $\phi_R$ ) using a Y-combiner. The Y-combiner acts as a comparator; if the circuit is fault-free, the test and reference signals are designed to have equal magnitude but opposite phase, resulting in destructive interference and a zero output. Any deviation from zero indicates a defect.
Component Design and Simulation: The DFT circuitry components—directional couplers, phase modulators, and Y-combiners—were designed and extensively simulated using Ansys Lumerical suites (FDE, varFDTD, FDTD, CHARGE, and INTERCONNECT).
- Directional Couplers: Designed as 3dB couplers with optimized waveguide gaps and lengths to ensure precise power splitting (targeting 50:50 distribution) while minimizing reflection losses.
- Phase Modulators: Modeled using the Drude expansion to calculate refractive index changes ( $\Delta n$ ) and absorption ( $\Delta \alpha$ ) based on carrier concentration changes induced by reverse-biased p-n junctions.
- MZM Assembly: Integrated directional couplers and phase modulators to create a switchable MZM. A 5mm modulation arm was selected to balance footprint and switching voltage (requiring ~5.6V for full switching), avoiding the impractical 16V requirement of shorter 3mm arms.
Validation Scenarios: The methodology was applied to two distinct PIC topologies:
- A feed-forward Optical Neural Network (ONN) where a standard MZI was replaced by the DFT MZM.
- An optical logic circuit with feedback loops (BCD-to-7-segment display), where the DFT circuit was inserted externally between nodes to avoid disrupting the closed-loop topology.

Key Contributions

DFT Architecture: The paper presents a novel DFT architecture specifically for silicon photonics that enables on-chip testing of signal power and phase against a reference.
Component Design: Detailed design and simulation of the constituent photonic components (3dB directional couplers, carrier-injection phase modulators, and Y-combiners) required to build the DFT circuit.
Fault Detection Demonstration: The authors demonstrate the ability to detect manufacturing defects (simulated as phase shifts or power deviations) in both feed-forward and feedback-loop circuit topologies.
Specification-Based Testing: The approach validates circuit operation by comparing actual signal characteristics against ideal specifications, rather than relying solely on pass/fail binary outcomes.

Results

Component Performance: The designed 3dB directional coupler achieved a 48:48 power distribution with minimized reflection. The 5mm MZM demonstrated an insertion loss of 2.6dB and an extinction ratio of 20.3dB.
ONN Testing: In the feed-forward ONN test, a fault-free circuit resulted in destructive interference (zero output) at the Y-combiner. When a defect was introduced (simulating a phase shift error of 2.14 rad instead of 3.14 rad), the MZM output changed to 0.1W, and the Y-combiner detected a non-zero signal, successfully identifying the malfunction.
Feedback Loop Testing: In the optical logic circuit with feedback loops, a defect introduced in a specific MZI caused a signal to appear at the test debug point. The DFT circuit successfully detected this deviation, confirming the methodology's applicability to complex topologies with cycles.

Significance and Claims
The paper claims that the proposed DFT methodology addresses the critical need for automated testing in the silicon photonics ecosystem. By embedding test-access and fault-detection circuitry directly onto the chip, the approach facilitates real-time data collection, failure detection, and post-fabrication tuning. The authors assert that this architecture can reduce testing time and costs, enhance testing coverage and reliability, and improve the scalability and yield of silicon PICs. The work serves as a foundational step toward a Computer-Aided Design (CAD) based testing infrastructure, bridging the gap between current manual calibration processes and the requirements for large-scale manufacturing of complex photonic systems. The authors note that while the DFT architecture is validated, the development of automatic tools for test-point selection and Automatic Test Pattern Generation (ATPG) remains a subject for future work.