PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation

Technical Summary: PANDA – An LLM-Enhanced Performance-Driven Analog Design Framework

Problem Statement
Traditional analog and mixed-signal (AMS) design automation remains fragmented, relying heavily on manual intervention across topology synthesis, transistor sizing, and layout generation. Existing approaches suffer from three primary limitations:

1. Lack of Intent Awareness: Conventional algorithms often perform inefficient, directionless exploration without understanding high-level design intent, frequently missing optimal design regions.
2. Stage Isolation: Schematic and layout stages are decoupled. Sizing is optimized without layout awareness, and layout tools lack structured links to circuit-level decisions, breaking optimization loops.
3. Inability to Iterate Autonomously: Existing flows cannot autonomously refine designs based on post-layout simulation results. Manual intervention is required to extract parasitics, re-evaluate performance, and adjust parameters, preventing true performance-driven refinement.

While recent Large Language Models (LLMs) offer potential for intent understanding, they lack a framework that preserves cross-stage dependencies and grounds generated plans in deterministic tool executions.

Methodology
PANDA addresses these challenges by employing an LLM as a central design coordinator that bridges high-level design intent to final physical layout. The framework unifies four tightly coupled stages into a coherent, dependency-preserving pipeline:

1. Framework Architecture: PANDA separates semantic planning from deterministic execution. The LLM interprets user intent, selects stage-specific actions, and generates machine-readable constraints. Specialized back-end engines execute physically grounded tasks (simulation, optimization, placement, routing). The workflow is implemented as reusable "Skills" connected via explicit handoff artifacts (e.g., JSON files), ensuring reproducibility and traceability.
2. Topology Synthesis: The framework invokes AnalogXpert to synthesize circuit topologies from structured requirements (function, performance targets, interface constraints). It generates a subcircuit-level SPICE netlist (.SUBCKT), parses it into structured artifacts (netlist, device relations, terminal mappings), and stores them in topology.json.
3. Analog Sizing: With the topology fixed, PANDA performs constrained optimization for transistor parameters (width, length, fingers, multipliers). It utilizes MOSTAR, a multi-stage hierarchical Bayesian optimizer. MOSTAR employs substructure-aware modeling (via L2G-GNN), symmetric constraints, and stage-adaptive acquisition to handle high-dimensional black-box objectives. The output is a parameter set saved as sizing.json.
4. Constraint-Driven Placement: The framework translates schematic structure and layout intent into geometry. It co-optimizes area/wirelength proxies, symmetry, collinearity, and signal/power-flow patterns. Legalization is applied to remove overlaps, producing a compact, routable solution stored in pl.json.
5. Routing and Layout Synchronization: The final stage aggregates outputs from previous stages to generate routing directives. It executes detailed routing using SAGERoute/SAGERoute2.0 under unified design-rule constraints. Crucially, PANDA maintains schematic-layout consistency by synchronizing LVS pin lists and iteratively updating routing configurations. After each attempt, it runs Parasitic Extraction (PEX) and post-layout simulation, feeding performance metrics back to the LLM to select and refine the best feasible solution.

Key Contributions
The paper outlines four primary contributions:

• Agentic Analog Design Flow: A unified pipeline connecting high-level design intent to physical implementation through four coordinated stages, preserving the dependency chain from circuit semantics to executable layout actions.
• LLM-Guided Topology Synthesis: A method to translate compact design intent and specifications into explicit structural artifacts (stable schematic representations) for downstream optimization.
• Substructure-Aware Analog Sizing: A multi-stage hierarchical Bayesian optimization engine that resolves device parameters from the generated topology and emits transistor-level artifacts directly consumable by layout tools.
• Constraint-Driven Layout Generation: A mechanism that combines placement and routing with schematic-layout synchronization, converting structural and sizing information into geometry-aware constraints and executable back-end actions.

Experimental Results
PANDA was evaluated on two case studies: a three-stage Operational Transconductance Amplifier (OTA) and a StrongARM Comparator (COMP).

• Execution Efficiency: The end-to-end runtime for a full PANDA run is in the range of several hours, a significant reduction compared to the days or weeks typically required for manual analog layout iterations.
• Design Quality (OTA): Post-layout results (via PEX) retained high gain (76.11 dB vs. target >75 dB) and robust phase margin (65.3° vs. target >60°). However, the Unity Gain Bandwidth (UGB) decreased from 10.84 MHz (pre-layout) to 4.192 MHz (post-layout) due to parasitics, indicating that while amplification behavior was preserved, the frequency target was not fully met post-layout.
• Design Quality (COMP): For the comparator, post-layout results showed a power consumption of 606.6 nW and a delay of 1.447 ns, compared to 469.9 nW and 1.0 ns pre-layout. This reflects the expected parasitic-induced overhead while remaining within a practical operating range.
• Traceability: The framework successfully generated traceable intermediate artifacts (e.g., topology.json, sizing.json, pl.json, rt.json) and structured prompts, demonstrating a clear progression from user intent to executable layout actions.

Significance
The paper claims that PANDA represents a significant step toward closing the loop in analog design automation. By shifting from isolated, algorithm-centric execution to an intent-centric, self-improving flow, PANDA bridges the gap between design intent and physical realization. It demonstrates a unified path toward practical analog design automation that reduces turnaround time while improving design performance through active management of cross-stage dependencies. The framework is released as open source to facilitate further research in this domain.