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APEIRON: composing smart TDAQ systems for high energy physics experiments

The paper introduces APEIRON, a distributed heterogeneous processing framework integrating hardware and software to enable smart trigger and data acquisition systems for high energy physics experiments, demonstrated through a particle identification application for the NA62 experiment.

Original authors: Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Pierpaol

Published 2026-07-03

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CC BY 4.0

Original authors: Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Pierpaolo Perticaroli, Cristian Rossi, Francesco Simula, Matteo Turisini, Piero Vicini

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are running a massive, high-speed train station where thousands of trains (data packets) arrive every second. Your job is to sort these trains, check their cargo, and decide which ones get to keep moving and which ones need to be stopped or redirected. In the world of high-energy physics, this "train station" is an experiment like NA62 at CERN, and the "trains" are particles smashing together.

The paper introduces APEIRON, a new "smart operating system" designed to build the brains of these train stations. Here is how it works, broken down into simple concepts:

1. The Problem: Too Big for One Brain

Traditionally, scientists used a single, super-smart computer chip (an FPGA) to do the sorting. But modern experiments produce so much data that one chip is like trying to manage a global airport with a single traffic controller. It gets overwhelmed.

Previously, if scientists needed more power, they had to manually connect multiple chips together, writing complex, custom code for every single connection. It was like building a bridge between islands by hand, one brick at a time, every time you needed a new island.

2. The Solution: APEIRON (The Universal Translator)

APEIRON is a framework that acts like a universal translator and automatic construction crew. It allows scientists to connect many chips together seamlessly without worrying about the messy wiring.

The "Hive Mind" Approach: Instead of one big brain, APEIRON creates a network of smaller brains (chips) that talk to each other instantly.
The "Post Office" System: It uses a smart routing system (like a highly efficient post office) that automatically decides which data packet goes to which chip. You don't need to know the address of every house; you just drop the letter in the mailbox, and the system handles the rest.
Simplicity for Scientists: Scientists can write their sorting rules in standard computer code (C++), and APEIRON automatically builds the complex hardware connections behind the scenes. It's like giving a chef a recipe and having a robot automatically assemble the kitchen, the stove, and the delivery trucks.

3. How It Moves Data (The Pipes)

The system moves data in two ways:

Inside the Chip: Data moves between different parts of the same chip through a local switch (like a hallway inside a house).
Between Chips: Data travels between different chips over high-speed "super-highways" (serial transceivers).
The Magic: The system uses "virtual channels" to prevent traffic jams (deadlocks), ensuring that even if thousands of data packets arrive at once, they never get stuck in a gridlock.

4. The Real-World Test: The NA62 Experiment

To prove it works, the team tested APEIRON on the NA62 experiment at CERN.

The Task: They needed to identify specific particles (kaons) by looking at the light they leave behind in a special detector (the RICH detector). This is like trying to identify a specific type of bird just by the pattern of its feathers, and you have to do it in a split second.
The Old Way: They previously used a mix of a GPU (a graphics card) and an FPGA, which was complicated and required custom hardware.
The APEIRON Way: They built a "FPGA-RICH" system entirely within the APEIRON framework. They used a "neural network" (a type of AI that learns to recognize patterns) to do the identification.

5. The Results: Fast and Efficient

The results were impressive:

Speed: The system processed data at a rate of 18.75 million events per second, easily beating the required speed of 10 million.
Efficiency: It used very little of the chip's resources (only 14% of the "logic blocks" and 2% of the "math processors"), leaving plenty of room for other tasks.
Accuracy: The AI successfully identified charged particles with high accuracy, though it noted that identifying electrons specifically was still a bit tricky (like distinguishing between two very similar-looking birds).

Summary

In short, APEIRON is a toolkit that lets physicists build massive, super-fast data-processing networks by simply writing code, without needing to be hardware engineers. It turns a complex, manual construction project into an automated, plug-and-play system, allowing them to handle the huge data floods of modern particle physics experiments with ease.

Technical Summary of APEIRON: Composing Smart TDAQ Systems for High Energy Physics Experiments

Problem Statement
Real-time dataflow processing in experimental particle physics demands high computing throughput, deterministic latency, and substantial I/O bandwidth. While Field-Programmable Gate Arrays (FPGAs) are well-suited to these requirements due to their reconfigurable logic and high-speed transceivers, a significant limitation exists in current High-Level Synthesis (HLS) environments: they are typically confined to single FPGA devices. When trigger or data acquisition (TDAQ) problems exceed the capacity of a single chip—a common scenario in modern experiments with high channel counts—developers are forced to rely on ad-hoc, manually crafted inter-FPGA communication layers. This gap between single-device HLS capabilities and the needs of multi-device real-time systems motivated the development of APEIRON.

Methodology and Architecture
APEIRON is a distributed heterogeneous processing framework designed to extend the Xilinx Vitis HLS ecosystem to operate transparently across a network of interconnected FPGAs. The framework spans the full software hierarchy, from low-level device drivers to a high-level dataflow programming model.

System Topology: The system models data paths as $m$ independent data sources feeding a cascade of $n$ stream-processing stages. These stages can reside on one or more FPGA nodes, with a network fabric recombining data streams as required. The underlying network is a packet-switched, dimension-order-routed mesh, allowing physical topology to be tailored via configuration rather than redesign.
Communication Infrastructure: Derived from APEnet and EXANEST network-on-chip designs, the communication subsystem supports both intra-node transfers (between kernels on the same FPGA) and inter-node transfers (across high-speed serial transceivers). Routing utilizes a crossbar switch with dimension-order routing and Virtual Cut-Through switching to ensure low latency. To prevent deadlock under dimension-order routing, two virtual channels are provided per physical link.
Programming Model: APEIRON employs a dataflow abstraction based on Kahn Process Networks. Developers write algorithmic C/C++ kernels that expose AXI4-Stream ports. Communication is handled via a lightweight C++ API featuring non-blocking send() and blocking receive() primitives. This API abstracts the underlying packet protocol, allowing kernels to communicate regardless of physical placement.
Build Flow: The mapping of the computational dataflow graph to the physical FPGA network is defined in a YAML configuration file. The APEIRON toolchain automatically generates all ancillary logic (routing, dispatching, aggregation) and produces the complete design bitstream, relieving designers of manual integration tasks.

Key Contributions
The paper presents the following core contributions:

A Modular Interconnect: A topology-configurable, low-latency direct interconnect among FPGA nodes.
Unified Abstraction: A dataflow programming model where tasks communicate via lightweight send/receive primitives, decoupling logical communication from physical placement.
Automation: A toolchain that automatically generates routing, dispatching, and aggregation logic from a compact application description, enabling users to focus solely on algorithmic kernels.
Target Versatility: A system capable of addressing both traditional low-level trigger systems and data-reduction stages in trigger-less or streaming readout setups.

Validation and Results
The framework was validated using a particle identification (PID) application for the NA62 experiment at CERN.

Context: The NA62 Ring Imaging Cherenkov (RICH) detector requires online PID to inform low-level trigger decisions. The authors replaced a previous heterogeneous GPU+FPGA pipeline (GPURICH) with a single-FPGA solution (FPGA-RICH) built entirely within APEIRON.
Implementation: The PID task was formulated as a neural-network inference problem using a seedless approach (relying only on RICH hit data). The architecture is a fully connected network (64-16-4 neurons). The model was quantized using QKeras and converted to synthesisable firmware via HLS4ML, utilizing fixed-point representations.
Performance: Synthesis on a Xilinx VCU118 board at 150 MHz resulted in a compact implementation using 14% of available LUTs and 2% of DSP slices. The measured inference latency was 146.66 ns, achieving a sustained throughput of 18.75 MHz, which comfortably exceeds the experiment's 10 MHz requirement.
Accuracy: Receiver Operating Characteristic (ROC) curves demonstrated satisfactory discriminating power for the multiplicity of charged particles ( $N_r$ ). Results for electron/positron ( $e^\pm$ ) identification were less satisfying, a limitation attributed to the RICH detector's inability to discriminate particle types outside the 15–35 GeV/c energy range.

Significance and Future Work
The paper claims that APEIRON addresses a recurrent need in particle physics TDAQ design by combining a configurable low-latency FPGA network with automated build tooling and a dataflow programming model. The successful deployment of FPGA-RICH demonstrates the framework's capability to deliver high-throughput, low-latency solutions for complex physics algorithms.

Future work focuses on improving the framework's performance and usability. Specifically, the authors aim to enhance $e^\pm$ identification results by integrating online primitives from the LKr calorimeter, which provides event energy information, thereby compensating for the limitations of the RICH detector alone.