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RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

The paper introduces RTL-Sequencer, a novel sequence-based paradigm that overcomes the limitations of existing graph-based methods for RTL timing prediction by linearizing logic cones and employing customized sequence models to achieve scalable and accurate early-stage timing optimization.

Original authors: Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie

Published 2026-07-20

📖 6 min read🧠 Deep dive

CC BY 4.0

Original authors: Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are building a massive, intricate city out of LEGO bricks. You want to make sure that when you flip a switch in the basement, the lights in the attic turn on instantly, without any flickering or delay. In the world of computer chips, this is called "timing." Engineers need to know exactly how fast a signal travels from one part of the chip to another. The problem is, for a long time, they could only check this timing after the entire city was built and the roads (wires) were paved. By then, if the lights were too slow, it was too late to fix the design without starting over, which wastes huge amounts of time and money.

To solve this, scientists have been trying to use "crystal balls"—computer programs that predict timing before the chip is built. They usually treat the chip's design like a giant map of connections, a "graph," where every brick is a dot and every wire is a line. They use smart algorithms to look at these maps and guess the timing. But these maps get so huge and tangled that the algorithms get confused, like trying to read a book where every sentence is written in a different language and the pages are shuffled. They struggle to see the long-distance connections that matter most.

This is where a new team of researchers from the Hong Kong University of Science and Technology steps in with a fresh idea. Instead of looking at the chip design as a tangled map, they decided to turn it into a story. They call their new tool RTL-Sequencer.

Turning a Tangled Knot into a Story

Think of a logic circuit (a small part of the chip) like a complex knot of yarn. Traditional methods try to study the whole knot at once, looking at how every strand touches every other strand. It's messy, slow, and hard to understand. The authors of this paper realized that if you pull the knot tight and lay the yarn out in a single, straight line, it becomes much easier to see how the signal flows from the start to the finish.

They call this process "linearizing." They take the 3D, tangled logic of the chip and arrange it into a 1D sequence, like a list of instructions or a line of dominoes falling one after another. By doing this, they can use powerful "sequence models"—the same kind of technology that helps computers understand human language or predict the next word in a sentence—to predict how fast the signal will travel.

Why the Old Way Was Stuck

The paper argues that the old "map" methods (Graph Neural Networks) have a few big problems. First, they can only see a short distance. If a signal has to travel through a very deep chain of logic, the map method gets blurry and forgets the beginning by the time it reaches the end. Second, they are computationally heavy. As the chip gets bigger, the time it takes to calculate the timing grows explosively, like trying to count every possible handshake in a stadium of people.

The authors suggest that these methods are missing the "direction" of the signal. In a chip, electricity flows one way (from input to output), but the old map methods often treat connections as if they could go both ways equally, which muddies the prediction.

The Four Magic Tricks of RTL-Sequencer

To make their "storytelling" approach work perfectly, the team didn't just line up the bricks; they added four special techniques to make the story even clearer:

Sequence Shuffling (The Mix-Up): Imagine you are teaching a student to read a story. If you always read the story in the exact same order, they might just memorize the order of the words instead of understanding the meaning. The researchers randomly shuffle the order of the bricks within each level of the design during training. This forces the AI to learn the actual logic and timing rules, not just the specific order they were given. It's like practicing a song by playing it in different keys so you really know the melody.
Bidirectional Modeling (Reading Backwards): Usually, we read a story from start to finish. But sometimes, to understand a sentence, you need to know what comes after it. The team built a system that reads the story forwards and backwards at the same time. This helps the AI understand how a signal at the end of the line affects the beginning, capturing the full picture of the signal's journey.
Differentiable Modeling (The Global vs. Local Filter): Sometimes, being too close to a neighbor makes you miss the big picture. In a chip, a signal might be influenced by a nearby brick, but the real timing depends on the long path it traveled. The team created a "filter" that subtracts the local noise (the immediate neighbors) from the global signal (the whole path). This ensures the AI focuses on the long, critical journey of the signal rather than getting distracted by local details.
Hybrid Architecture (The Best of Both Worlds): While the "story" approach is great for long paths, it's sometimes weak at seeing the immediate neighborhood of a brick. So, they combined their story-telling AI with a "map" AI (a Graph Neural Network) for the local details. It's like having a tour guide who knows the whole city's history (the sequence) but also has a local map to show you the best coffee shop on the corner (the graph).

The Results: Faster and Smarter

When the team tested RTL-Sequencer against the best existing tools, the results were impressive. In their simulations, their new method predicted the "Arrival Time" (when the signal gets there) with an error rate of just 17.24%, which was significantly better than the next best method, which had an error of 20.29%.

More importantly, the paper shows that their method scales much better. While the old "map" methods get stuck and slow down when the chip designs get huge (with millions of parts), RTL-Sequencer keeps its speed steady. It handles deep, complex designs without getting overwhelmed, proving that turning a tangled knot into a straight story is a winning strategy.

The authors conclude that this approach opens the door for much faster and more accurate chip design. By predicting timing early in the process, engineers can fix problems before the chip is even built, saving time and resources. While this is a simulation-based study, the results suggest that shifting from "maps" to "stories" could be the future of how we design the brains of our computers.

Technical Summary: RTL-Sequencer

Problem Statement

Accurate timing prediction at the Register-Transfer Level (RTL) is a critical bottleneck in digital integrated circuit design automation. Traditional methodologies rely on post-layout Static Timing Analysis (STA), which requires accurate physical information (e.g., wire lengths) unavailable during early design phases. This delay forces timing-driven optimizations to occur late in the design cycle, leading to extended iterations and increased time-to-market.

While Machine Learning (ML) has been applied to early-stage timing prediction, existing approaches face significant limitations when applied to RTL designs, which are represented as Boolean Operator Graphs (BOGs). These designs often involve deep, large-scale logic cones (exceeding 10,000 nodes with depths >100). Current graph-based methods struggle with:

Limited Receptive Fields: Graph Neural Networks (GNNs) are bounded by network depth, failing to capture long-range timing dependencies in deep cones.
Over-smoothing: Stacking layers to increase depth often leads to homogenized node embeddings.
Computational Complexity: Graph Transformers (GTs) and propagation-based methods suffer from quadratic complexity relative to node count or cone depth, hindering scalability.
Loss of Directionality: Many graph models treat relationships as undirected or fail to explicitly preserve signal directionality, which is crucial for timing analysis.

Methodology: RTL-Sequencer

The authors propose RTL-Sequencer, a novel framework that shifts from graph-based modeling to a sequence-based paradigm. The core insight is that logic cones can be linearized into ordered node sequences, allowing the application of modern linear sequence models that offer global receptive fields with linear computational complexity.

1. Basic Framework

Cone Extraction: The RTL design is transformed into a BOG. Logic cones are extracted as transitive fan-in subgraphs rooted at endpoint registers.
Linearization: An inverse Breadth-First Traversal (BFT) converts each cone into a node sequence. Unlike Depth-First Traversal, BFT preserves the hierarchical progression of signal propagation.
Sequence Modeling: The sequence is processed by a "Sequencer" model (e.g., Mamba-2) to update node representations based on historical context, avoiding the quadratic complexity of attention mechanisms.

2. Synergistic Techniques

To address the sub-optimality of deterministic BFT and standard sequence models, four specific techniques are introduced:

Sequence Shuffling: To prevent the model from overfitting to a fixed node ordering (which discards topological information), nodes within each BFT depth level are randomly permuted during training (50% probability). This acts as data augmentation, exposing the model to diverse topological variants while preserving logical dependencies. During inference, a heuristic deterministic ordering based on in/out-degree statistics is used.
Bidirectional Sequence Modeling: To capture the bidirectional nature of signal propagation and allow later nodes to influence earlier representations, the framework employs both forward and backward sequence models. The hidden states are aggregated to enrich the representation of each node.
Differentiable Sequence Modeling: Standard BFT places unrelated nodes at the same depth adjacent to each other, causing sequence models to overemphasize local depth-specific structures. A differentiable mechanism is introduced to subtract "depth-local" embeddings (computed via separate models on depth-specific subsequences) from "global" embeddings. A learnable coefficient ( $\lambda$ ) controls this subtraction, ensuring the final representation aligns with global timing behavior rather than local depth artifacts.
Hybrid Graph-Sequence Architecture: To leverage the strengths of both paradigms, the framework integrates GNNs (specifically GatedGCN) within the sequence pipeline. The sequence is first processed by GNNs to capture localized structural dependencies, then converted back to a sequence for long-range dependency modeling. All transitions are differentiable, enabling end-to-end training.

Key Contributions

Paradigm Shift: The first proposal of a sequence-based paradigm for RTL timing prediction, replacing graph-based models to achieve global receptive fields with linear complexity and explicit signal directionality.
Customized Techniques: The design of four synergistic techniques (shuffling, bidirectional modeling, differentiable modeling, and hybrid architecture) specifically tailored to overcome the challenges of linearizing logic cones.
Empirical Validation: Extensive experiments demonstrating superior performance over state-of-the-art (SOTA) baselines, including GNNs, Graph Transformers, and propagation-based methods.

Experimental Results

The framework was evaluated on 21 open-source RTL designs (ranging from 6K to 510K gates) using 5-fold cross-validation. Ground truth was obtained via Synopsys PrimeTime after physical implementation.

Performance: RTL-Sequencer achieved the lowest Mean Absolute Percentage Error (MAPE) and highest correlation scores across all metrics (Arrival Time, Worst Negative Slack, Total Negative Slack).
- Arrival Time (AT): MAPE of 17.24% (vs. 20.29% for the next best, CircuitFusion) and $R=0.92$ .
- Worst Negative Slack (WNS): MAPE of 17.66% ( $R=0.91$ ).
- Total Negative Slack (TNS): MAPE of 23.92% ( $R=0.88$ ).
Scalability: Unlike GNNs (which suffer from over-smoothing in deep cones) and Graph Transformers (which exhibit quadratic memory overhead), RTL-Sequencer maintains linear memory complexity with respect to node count and cone depth, enabling training on deeply structured designs.
Ablation Studies: Removing any of the four proposed techniques resulted in performance degradation. Sequence shuffling provided the most significant gain, highlighting the importance of structural data augmentation.

Significance and Claims

The paper claims that RTL-Sequencer represents a fundamental shift from isotropic graph representations to directional sequence modeling. By linearizing logic cones, the framework successfully addresses the scalability and receptive field limitations of existing graph-based methods. The results suggest that sequence-driven frameworks are a robust alternative for early-stage timing estimation, potentially reducing design iterations and accelerating time-to-market by enabling accurate timing predictions before the layout stage. The work does not claim to replace physical STA but rather to provide a highly accurate, scalable proxy for early design optimization.