← Latest papers
🤖 machine learning

CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

CoEvoP&R is a novel framework that leverages large language models to automatically evolve readable, differentiable placement objectives guided by routing and timing feedback, significantly improving post-route wirelength, congestion, and timing metrics compared to native analytical placers.

Original authors: Ruogu Chen, Weihua Xiao, Ramesh Karri, Jie Han

Published 2026-07-21
📖 4 min read☕ Coffee break read

Original authors: Ruogu Chen, Weihua Xiao, Ramesh Karri, Jie Han

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to pack a suitcase for a trip, but you have a strict rule: you must arrange everything so that it fits perfectly, looks neat, and is easy to grab when you arrive. In the world of computer chips, this "suitcase" is the silicon die, and the "items" are billions of tiny electronic components. The process of arranging these components is called placement. If you pack them poorly, the wires connecting them become too long, traffic jams (called congestion) happen, and the chip runs too slow or uses too much power.

To solve this, engineers use smart computer programs called analytical placers. These programs try to find the best arrangement by minimizing a "score" or "objective function." Think of this score like a recipe for a perfect packing job. Traditionally, this recipe only cares about how short the wires are and how evenly the items are spread out. However, there's a catch: a short wire on the drawing board doesn't always mean a fast chip in real life. The real test comes later, when the wires are actually built and the chip is tested for speed. If the recipe is too simple, the final product might fail the speed test, forcing engineers to start over. For years, experts have tried to fix this by manually tweaking the recipe or using "black box" AI that works well but is impossible to understand or fix when it goes wrong.

This is where a new approach called CoEvoP&R comes in. It's like giving a creative, super-smart robot chef a cookbook and asking it to invent a new recipe that guarantees a perfect suitcase, not just a neat one. The paper introduces a framework that uses a Large Language Model (LLM)—the same kind of technology behind advanced chatbots—to automatically evolve and improve these placement recipes. Instead of a human guessing what the perfect formula should be, the LLM acts as a curious explorer. It proposes a new "objective function" (a mathematical formula), tests it on a simulated chip, and then checks the results against real-world routing and timing tools. If the new formula makes the wires shorter and the chip faster, the LLM learns from that success. If it fails, the LLM learns from the mistake.

The researchers found that this method works surprisingly well. By letting the AI "evolve" the rules for packing chips, they were able to significantly improve the final quality of the chip design. On a set of standard test designs, the new method reduced the length of the wires connecting the components by 16.9% and cut down on traffic jams (congestion) by 36.7% compared to the standard method. Even more impressively, it improved the chip's speed, making the worst-case timing delay better by 0.70 nanoseconds and fixing a massive 912 nanoseconds of total timing delay. The team also tested these evolved recipes on different types of chips and found they still worked well, reducing wire length by 5.4% and congestion by 23.2% on other designs.

What makes this special is that the AI isn't just a mysterious black box; it writes out the actual mathematical formulas in a way humans can read and understand. It learns by keeping a "memory" of what worked and what didn't, using that history to guide its next attempt. The paper suggests that this approach bridges the gap between the initial packing plan and the final, real-world performance of the chip, offering a way to automatically discover better design rules without needing a human expert to manually tweak every single variable. It's a step toward computers that can not only follow instructions but also invent better ways to solve complex physical problems.

Drowning in papers in your field?

Get daily digests of the most novel papers matching your research keywords — with technical summaries, in your language.

Try Digest →