SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
The paper proposes SCALE, a self-supervised framework that leverages a generative language model to create synthetic DRC-violation data and fine-tune a domain-adapted vision-language model, thereby significantly improving the success rate of local place-and-route design-rule violation fixing at advanced sub-2nm semiconductor nodes.
Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer
Imagine you are trying to build a skyscraper out of microscopic Lego bricks, but the instructions are written in a secret language that changes every time you blink. This is the world of modern chip design, where engineers are trying to fit billions of tiny transistors onto a silicon chip smaller than a fingernail. As these chips get smaller—entering the "sub-2nm" era, which is smaller than the width of a single virus—the rules for how the bricks can touch, overlap, or sit next to each other become incredibly complicated. These rules, called "design rules," are like a hyper-strict building code: if two wires are too close, the chip might short-circuit; if a hole is too small, electricity can't flow. Checking for these mistakes is called "Design Rule Checking" (DRC), and fixing them is a nightmare. If a computer finds a mistake, it usually just points at it and says, "Wrong!" leaving human engineers to guess how to fix it without breaking something else nearby.
Recently, scientists have been teaching computers to be smarter using "Large Language Models" (LLMs)—the same kind of AI that can write stories or code. But there's a catch: these AIs are great at reading text but terrible at understanding pictures of complex geometry. If you show a standard AI a picture of a chip layout, it might hallucinate (make things up), counting the wrong number of holes or missing a tiny gap that causes a disaster. The big question was: Can we teach an AI to not only see the chip but also understand the secret building code and fix the mistakes automatically?
This is exactly what the researchers behind the paper "SCALE" set out to solve. They realized that to teach an AI to fix these tiny chips, they first needed to create a massive library of "mistakes" to practice on. But here's the problem: real chips are usually perfect (they've already been checked), so there are almost no real pictures of broken chips to show the AI. To get around this, the team built a clever two-step system. First, they taught a computer to act like a creative writer that can "imagine" broken chip layouts. They fed it text descriptions of chip parts and asked it to fill in the blanks, creating thousands of new, realistic-looking chip designs that might have violations. Then, they used a super-strict industrial checker to scan these imaginary designs and label exactly where the rules were broken. This gave them a huge dataset of "broken chips" with the correct answers.
Using this new library, they trained a special "expert" AI (a Vision-Language Model) to look at a chip layout, spot the violation, and explain why it broke the rules, just like a senior engineer would. Finally, they hooked this expert AI up to a standard coding robot. When the robot found a problem, the expert AI would whisper the solution: "Hey, move this wire two nanometers to the left, but don't touch that neighbor." The results were impressive. On 100 real-world chip designs that were having trouble, this team-up solved between 12% and 25% more problems than the coding robots could solve on their own, reaching a success rate of up to 97%.
The paper explicitly argues against the idea that off-the-shelf AI models (like the ones you might chat with online) are ready for this job. They showed that without special training, these models often "hallucinate" features, like counting the wrong number of connection points or misunderstanding the spacing rules, leading to fixes that create even more errors. They also ruled out the idea that you can just write a script to generate these mistakes; their simulations showed that simple scripts produce boring, repetitive patterns that don't look like real chips, whereas their self-supervised method created a diverse, realistic variety of problems.
The authors are quite confident in their findings because they tested this on actual, real-world chip designs from a sub-2nm technology node, not just on made-up simulations. They measured the success rate by seeing if the final chip passed all the strict industrial checks without introducing new errors. While they suggest this method could be used for other tricky chip design tasks in the future, their current results are specific to fixing local layout errors. They found that by combining a text-based AI (to generate the practice data) with a vision-based AI (to analyze the images), they could bridge the gap between general AI and the highly specific, secret rules of chip manufacturing, making the process of fixing these microscopic skyscrapers much faster and more reliable.
Drowning in papers in your field?
Get daily digests of the most novel papers matching your research keywords — with technical summaries, in your language.