Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

In the world of modern electronics, the tiny chips that power our devices are designed through a complex, iterative process. Engineers start with a logical blueprint and gradually transform it into a physical layout, a journey that involves placing billions of microscopic components and connecting them with microscopic wires. A critical checkpoint in this journey is a safety check called static timing analysis. This process ensures that electrical signals travel fast enough between components to keep the device functioning correctly. However, a significant challenge arises early in the design phase, before the wires are fully drawn. At this stage, engineers have a rough idea of where components will sit, but they lack precise details about the wires that will connect them. Without these details, traditional tools often have to guess the travel time of signals. To be safe, these tools tend to guess conservatively, assuming the signals will be slower than they likely will be. This caution, while preventing errors, often leads to over-design, where circuits are made larger and consume more power than necessary just to compensate for uncertainty.

Researchers at the Universidad de Costa Rica have developed a new method to solve this guessing game, offering a way to predict signal travel times with much greater accuracy before the final wiring is complete. Instead of relying on the conservative guesses of standard software or on massive, complex computer models that are difficult to understand, they created a lightweight, hybrid system. This system combines two simple, well-understood mathematical techniques: a decision tree, which sorts data into groups based on specific rules, and linear regression, which finds straight-line patterns within those groups. By using the decision tree to organize the messy, real-world data into smaller, more manageable chunks, and then applying a simple line-fitting formula to each chunk, the researchers built a model that learns from past designs to predict future ones. Their approach is not only highly accurate but also transparent, allowing engineers to see exactly why a prediction was made, a feature often missing in more complex artificial intelligence systems.

The team tested their new method using the open-source design tool OpenLane, which is widely used by researchers and hobbyists to create integrated circuits. They fed the model data from various circuit designs, including standard benchmarks and real-world examples, teaching it to recognize how factors like the distance between components, the size of the gates, and the number of connections influence signal speed. The results were striking. When compared to the standard estimates provided by the OpenLane tool, the new hybrid model reduced the error in delay predictions by up to 80 percent. Even when the model was stripped of specific details about the OpenLane tool itself, it still improved accuracy by 71 percent. In practical terms, this means that designers can now trust their early-stage estimates much more, potentially avoiding the need for multiple rounds of costly rework later in the design process.

Beyond raw accuracy, the researchers highlighted the efficiency and clarity of their solution. The model they built is incredibly small, occupying just over 10 megabytes of storage, whereas other similar machine learning models used in this field can require several gigabytes. It is also significantly faster, running more than twice as quickly as comparable models, and it is over 300 times smaller in size. Perhaps most importantly for the engineering community, the model is explainable. Because it relies on a decision tree followed by simple linear equations, an engineer can trace the path of a prediction: they can see which rules the data followed and how the final calculation was derived. This stands in contrast to many modern machine learning tools that act as "black boxes," offering answers without revealing the reasoning behind them.

The study confirms that this hybrid approach offers a viable alternative to the heavy, opaque models often used in chip design. By breaking the problem down into smaller, linearly predictable parts, the system captures the complex, non-linear behaviors of real circuits without needing a massive neural network. The researchers noted that the model performed exceptionally well on certain circuits, reducing prediction errors by as much as 80 percent for specific designs, suggesting that the method is particularly effective when the new designs share similarities with the data used to train it. While the current work focused on a specific set of open-source tools and technology nodes, the success of this lightweight, transparent method suggests a promising path forward. It demonstrates that in the high-stakes world of chip design, sometimes the most effective tools are not the most complex ones, but rather those that are precise, fast, and easy to understand.