An Equivalence-Checked RV32IM Pipeline with Integrated gshare Branch Prediction and On-FPGA Visualization

Technical Summary: An Equivalence-Checked RV32IM Pipeline with Integrated gshare Branch Prediction and On-FPGA Visualization

Problem Statement
The paper identifies two persistent practical gaps in the ecosystem of open-source RISC-V soft cores, which hinder their utility for both education and research. First, the internal pipeline behavior of existing cores is typically observable only through external host-PC instrumentation (such as waveform dumps or in-system ILAs), which couples observation to specific workstations and tool protocols. Second, performance-critical features like dynamic branch prediction are rarely integrated into compact open-source cores, and when present, they are seldom quantitatively characterized on a per-benchmark basis with rigorous verification.

Methodology
The authors present a synthesizable five-stage RV32IM pipeline designed to address these gaps through a unified architecture. The methodology encompasses three primary technical components:

1. Microarchitecture: The core implements the RV32I base integer instruction set plus the MUL instruction from the M extension. It utilizes a classical five-stage in-order pipeline (IF, ID, EX, MEM, WB) with separate forwarding and hazard detection units. A key feature is the integration of a wired-in gshare branch predictor (64-entry pattern history table, 6-bit global history register) with a configurable mode parameter. This allows the same RTL to operate in either a static "not taken" mode or a full dynamic gshare mode, enabling controlled performance comparisons.
2. Non-Intrusive Observability: A dedicated, read-only introspection unit taps signals from the functional datapath (including pipeline registers, the architectural register file, and predictor counters). These signals drive a hardware-resident VGA renderer that displays live pipeline state, register contents, and prediction statistics on a directly attached monitor. Crucially, this unit has no output signals that re-enter the datapath, ensuring the observation mechanism does not alter the core's execution behavior.
3. Verification Framework: Functional correctness is established via bit-exact equivalence checking. The authors developed an independent Python golden ISA simulator (implementing the same RV32I+MUL subset) to serve as a reference. The synthesisable RTL is simulated against this golden model across a six-program benchmark suite. Acceptance is defined by bit-identical agreement on the architectural register file and data memory.

Key Contributions
The paper contributes a single coherent design that closes the identified gaps:

• Host-Free Visualization: A novel architecture that renders full pipeline state and predictor metrics on a commodity display without requiring a host PC, JTAG, or ILA.
• Controlled Branch Prediction Analysis: The integration of a gshare predictor with a static/dynamic mode switch, allowing for direct measurement of IPC improvements and misprediction penalties within the same hardware design.
• Rigorous Verification: A methodology that validates the RTL against an independently authored golden simulator, ensuring that the complex pipeline and prediction logic adhere strictly to the ISA specification.

Experimental Results
The design was implemented on a Xilinx Artix-7 (xc7a100t-1) FPGA.

• Performance: The bare core synthesizes to a post-route frequency of 65.3 MHz.
• Resource Utilization: The implementation occupies 17,315 LUTs (27.3% of the device) and 39,119 flip-flops (30.9%). The resource cost is dominated by the multiplexers required for the VGA renderer's register file snapshot, rather than the datapath itself.
• Branch Prediction Impact: Across six benchmarks with mixed branch behaviors, enabling the gshare predictor yielded a mean 2.33× improvement in Instructions Per Cycle (IPC) compared to a static "not taken" baseline (ranging from 1.36× to 2.82×). Prediction accuracy ranged from 95.5% to 99.4%.
• Correctness: All six benchmarks passed the equivalence check, confirming bit-identical register and memory states between the FPGA-simulated RTL and the Python golden model.

Significance and Claims
The authors position this work not as a record-breaking achievement in clock frequency or area efficiency, but as a complete, equivalence-checked, and silicon-verified design point that uniquely combines three features rarely found together in open-source soft cores: (a) wired-in dynamic branch prediction with per-benchmark characterization, (b) bit-exact equivalence checking against an independent reference, and (c) host-PC-free observation of pipeline state on a directly attached monitor.

The paper claims that this design is particularly valuable for computer-architecture education, where students can observe pipeline hazards and branch prediction effects on the actual silicon executing the code, and for lightweight FPGA-based architectural research, where credible claims about micro-architectural overhead require both RTL-level equivalence and post-place-and-route measurements. The authors note that the design is conservative in its ISA support (RV32I + MUL only, no exceptions/interrupts) and memory size, prioritizing the demonstration of the observability and verification methodology over general-purpose workload capability.