2-Terminal refresh-free memory for high-density and low power consumption during data retention
This paper proposes a high-density, low-power 2-terminal refresh-free memory cell for 1T-DRAM applications that utilizes a multilayer Si/SiGe nanowire structure with a polysilicon layer and buffer to achieve excellent data retention, fast operation speeds, and minimal standby current.
Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer
In the world of modern computing, the memory that holds your active data is a delicate balancing act between speed, size, and power. This is the domain of dynamic random-access memory, or DRAM, the workhorse that keeps your computer running smoothly. For decades, engineers have made these memory cells smaller and smaller to fit more information into a single chip. However, as these cells shrink, they struggle to hold onto their electrical charge long enough to be useful. To prevent the data from fading away, the computer must constantly "refresh" the memory, checking and recharging each cell thousands of times a second. This process consumes a significant amount of energy and slows down the system, creating a bottleneck as devices demand more capacity. Researchers have tried various fixes, such as building taller, more complex structures or using special insulating materials, but these often make manufacturing too difficult or expensive. The ideal solution would be a memory cell that can hold its state without needing constant refreshing, using very little power, and fitting into a tiny space with just two electrical connections.
A team of researchers at Pohang University of Science and Technology and Samsung Electronics has proposed a new design that aims to solve this problem. They have developed a two-terminal memory cell that can retain data without the need for periodic refreshing, all while consuming a minuscule amount of power. The device is built as a tiny nanowire, a microscopic strand of material with a cross-sectional area of 20 × 20 nm². Inside this wire, the scientists have arranged a specific sequence of layers: a silicon core, a storage section made of silicon-germanium, and a buffer layer, all wrapped in a surrounding shell of polysilicon. This architecture allows the cell to occupy a very small footprint, making it suitable for high-density memory chips, but the true innovation lies in how it manages the flow of electrical charge.
The core challenge in this type of memory is keeping positive electrical charges, known as holes, trapped in the storage region long enough to represent a "one" state. In previous designs, these charges would leak away quickly or require a high voltage to maintain, leading to high power consumption. The new device uses a clever trick involving the materials themselves. By placing the silicon-germanium storage region next to pure silicon, the researchers created a natural energy barrier that acts like a dam, preventing the holes from diffusing out of the storage area. This barrier ensures that the data stays put even when the voltage is lowered. Furthermore, the surrounding polysilicon layer helps guide the electrical potential so that the holes accumulate exactly where they are needed, rather than spreading out uselessly. This precise control allows the device to maintain the "one" state with a holding current as low as 4.5 picoamperes, a value so small it is barely measurable, yet sufficient to keep the data alive.
One of the most significant findings in this study is the ability to operate with a gentle, gradual slope in current behavior. In many similar devices, the transition between holding data and losing it is very steep, meaning that tiny variations in manufacturing or voltage could cause the memory to fail or consume too much power. The new design offers a wide margin of safety, with a current slope of 220 millivolts per decade. This stability is crucial for large memory arrays where thousands of cells are connected together, as it ensures that the power consumption remains low and consistent across the entire chip. The researchers also demonstrated that the device can switch states quickly, performing write and read operations in less than 10 nanoseconds. This speed is comparable to current high-performance memory, proving that eliminating the refresh requirement does not come at the cost of performance.
To ensure the memory can be reset reliably, the team introduced a buffer layer within the nanowire structure. When writing a "zero," the device needs to clear out the stored holes. Without this buffer, the electrical field could become too concentrated, accidentally generating new holes and preventing the memory from being erased properly. The buffer layer smooths out this electrical field, allowing the holes to recombine and disappear cleanly. This mechanism ensures that the device can switch between states rapidly and accurately, with the "zero" state being clearly distinguishable from the "one" state by a ratio of over one million to one. The entire system was modeled using advanced computer simulations that accounted for the complex physics of electron movement and charge generation, confirming that the design works as intended based on technology computer-aided design (TCAD) simulation.
This work represents a significant step toward a new generation of memory that does not rely on the constant energy drain of refreshing. By combining a simple two-terminal structure with sophisticated material engineering, the researchers have shown that it is possible to create a memory cell that is both dense and energy-efficient. The device successfully retains data for extended periods using only a tiny trickle of power, while still offering the fast speeds required for modern computing. If these designs can be manufactured at scale, they could lead to computers and mobile devices that run longer on a single battery and process data more efficiently, addressing the growing energy demands of the digital age. The study confirms that through careful manipulation of energy barriers and charge flow, the limitations of traditional memory can be overcome without sacrificing speed or density.
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