⚛️ quantum physics

PACOX: A FPGA-based Pauli Composer Accelerator for Pauli String Computation

This paper introduces PACOX, the first dedicated FPGA-based accelerator that utilizes a compact binary encoding and parallel pipelined architecture to efficiently compute Pauli strings, significantly outperforming state-of-the-art CPU methods in speed, memory usage, and energy efficiency for hybrid quantum-classical algorithms.

Original authors: Tran Xuan Hieu Le, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima

Published 2026-01-27

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CC BY 4.0

Original authors: Tran Xuan Hieu Le, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to solve a massive, complex puzzle where every piece represents a tiny quantum particle. In the world of quantum computing, these pieces are called Pauli strings. To make sense of the puzzle, a computer has to shuffle these pieces around and flip their colors (phases) according to strict rules.

The problem is that as you add just a few more pieces to the puzzle, the number of ways they can be arranged explodes. It's like trying to find a specific grain of sand on a beach that doubles in size every time you add a single grain. Traditional computers (CPUs) get overwhelmed by this exponential growth, becoming slow and hungry for electricity.

Enter PACOX: The Specialized Puzzle Solver

The paper introduces PACOX, a custom-built "accelerator" chip designed specifically to handle these Pauli strings. Think of PACOX not as a general-purpose computer, but as a specialized assembly line built inside a reconfigurable factory (an FPGA).

Here is how it works, using simple analogies:

1. The "XOR" Shortcut (The Magic Translation)

Normally, calculating these quantum strings is like doing heavy math with giant numbers. PACOX changes the rules. It translates the problem into a simple game of "Same or Different" (which mathematicians call XOR).

The Analogy: Imagine you have a row of light switches. Instead of calculating complex equations to see which lights are on, you just ask: "Is this switch the same as that one?" If yes, turn it off; if no, turn it on.
The Result: This turns heavy, slow math into lightning-fast logic checks. The paper claims this allows the chip to skip the "heavy lifting" and just do the shuffling instantly.

2. The Assembly Line (Parallel Processing)

A standard computer is like a single chef trying to chop 1,000 onions one by one. PACOX is like a kitchen with 32 chefs (called Processing Elements) working side-by-side.

The Analogy: Instead of one person doing the whole job, PACOX splits the massive list of tasks into 32 tiny chunks. Each chef handles their own chunk simultaneously.
The Result: Because they work in parallel, the job gets done roughly 32 times faster than if one person did it alone.

3. The Compact Backpack (Memory Efficiency)

As the puzzle gets bigger, the memory needed usually grows so fast it crashes the computer.

The Analogy: Imagine you need to carry a library of books. A normal computer tries to carry the whole library in a giant, heavy truck. PACOX, however, uses a "compression trick." It realizes that most of the books are empty pages, so it only packs the pages with writing into a tiny, lightweight backpack.
The Result: The paper shows that for a 32-qubit problem, other methods need about 50 gigabytes of memory (a huge truck), while PACOX only needs about 18 gigabytes (a manageable backpack).

The Real-World Test Results

The researchers built this system on a specific chip called the Xilinx ZCU102 and tested it against the best software running on powerful Intel computers.

Speed: PACOX was significantly faster. For larger puzzles (up to 19 qubits), it was up to 2 million times faster than some older methods. It's like finishing a marathon in the time it takes a snail to cross a sidewalk.
Energy: Because it works so efficiently, it uses very little power. The chip itself consumed only 0.33 Watts while running at full speed.
- The Analogy: If a standard computer is a gas-guzzling truck, PACOX is a highly efficient electric scooter. It does the same job but with a fraction of the fuel.
The Bottleneck: The only thing slowing PACOX down slightly was the "delivery truck" (data transfer) between the chip and the main computer. The chip is so fast that it sometimes has to wait for the data to arrive, but the chip itself is never the problem.

Summary

In short, PACOX is a specialized hardware tool that solves a specific quantum math problem by:

Turning hard math into simple "yes/no" logic.
Using 32 workers to do the job at the same time.
Packing data tightly to save space.

The paper concludes that this approach makes hybrid quantum-classical systems (where a quantum computer talks to a regular computer) much faster and more energy-efficient, specifically for the task of handling Pauli strings.

Technical Summary: PACOX – A FPGA-based Pauli Composer Accelerator

Problem Statement
Pauli strings serve as a fundamental computational primitive in hybrid quantum-classical algorithms, including Hamiltonian simulation, variational quantum algorithms, and quantum error correction. However, the classical computation of these strings faces significant scalability challenges. As the number of qubits ( $n$ ) increases, the computational cost grows exponentially, quickly becoming a performance bottleneck. Existing software-based solutions (e.g., Qiskit, PennyLane) and optimized CPU methods (e.g., tree-based approaches, recursive matrix slicing) struggle with large $n$ due to exponential memory growth and limited arithmetic throughput. While GPU-based approaches offer improvements, they still face scalability limitations. Furthermore, existing FPGA implementations in quantum systems primarily focus on control or circuit-level emulation, lacking dedicated hardware for the specific task of Pauli string computation, which involves complex index transformations and phase accumulation.

Methodology
To address these limitations, the authors propose PACOX (PAuli COmposer X Accelerator), the first dedicated FPGA-based accelerator for Pauli string computation. The methodology is built upon three core innovations:

Algorithmic Reformulation: The authors adapt the Pauli Composer (PC) algorithm [11] by reformulating operator evaluation. Instead of performing expensive matrix multiplications, PACOX utilizes a compact binary encoding that transforms the computation into XOR-based index permutation and phase accumulation. This approach replaces multiplication with XOR logic, significantly reducing computational cycles and hardware complexity.
Parallel and Pipelined Architecture: The hardware design employs a cluster of 32 Processing Elements (PEs) organized on a Xilinx ZCU102 FPGA. The algorithm is parallelized such that the $2^n$ data vectors are partitioned and streamed to the PEs. Each PE independently updates assigned entries using an Arithmetic Logic Unit (ALU) within a single clock cycle. The architecture supports a pipelined execution strategy where data is processed in segments, reducing execution time by a factor proportional to the number of PEs compared to sequential implementations.
Optimized Memory Organization: To manage the exponential growth of data, PACOX implements a specialized memory hierarchy consisting of Context Buffers and an n-Pauli Matrix Memory. The design stores only nonzero elements and utilizes 2-bit encodings for values (representing $1, -1, 1j, -1j$ ) rather than 32-bit values, drastically reducing memory footprint. The system uses a 64-bit PIO interface for configuration and a DMA controller with an AXI Mapper to handle data transfer between the Processing System (PS) and the Programmable Logic (PL).

Key Contributions

First Dedicated Hardware Accelerator: PACOX is presented as the first FPGA accelerator specifically designed for Pauli string computation, filling a gap left by existing FPGA solutions focused on control or emulation.
XOR-Based Computation: The paper introduces a novel formulation that replaces arithmetic multiplication with XOR operations via binary encoding, enabling high-speed, low-power logic implementation.
Scalable PE Cluster: The design demonstrates a scalable, parallel architecture capable of handling up to 19 qubits efficiently on a mid-range FPGA, leveraging data-level parallelism to overcome sequential bottlenecks.
Memory Efficiency: By storing only nonzero entries and using compact encoding, the design significantly lowers memory requirements compared to state-of-the-art CPU and GPU methods.

Experimental Results
The PACOX design was synthesized and implemented on a Xilinx ZCU102 FPGA using Vivado 2021.2.

Resource Utilization: The design operates at 250 MHz, utilizing 8,052 LUTs, 10,934 FFs, and 324 BRAMs.
Power Efficiency: The dynamic power consumption for the accelerator is 0.33 W, with a total system power of 2.58 W during execution.
Performance vs. CPU: For Pauli strings up to 19 qubits, PACOX consistently outperforms state-of-the-art CPU-based methods (including PC, Algo993, and Tree algorithms) running on an Intel i9-10940X.
- Speedup: PACOX achieves speedups ranging from 4.15x to 9x compared to the PC algorithm, and up to 2 million times faster compared to the Tree method for larger $n$ .
- Power-Delay Product (PDP): PACOX demonstrates superior energy efficiency, with PDP improvements ranging from 3.14x to 60.1x over the PC method, and up to $6.06 \times 10^7$ times better than the Tree method.
Software Comparison: In tests against Qiskit and PennyLane libraries across various datasets (Heisenberg, QChem, TFIM, Stabilizer), PACOX consistently showed lower execution times and PDP values, with the performance gap widening as qubit count increased.
Bottleneck Analysis: The authors note that while execution time scales efficiently, total runtime is currently limited by data transfer bandwidth (4 GB/s on ZCU102), where transfer time dominates computation time for larger datasets.

Significance and Claims
The paper claims that PACOX delivers a high-speed and energy-efficient hardware solution for Pauli-based workloads in hybrid quantum-classical systems. By demonstrating that dedicated FPGA acceleration can overcome the exponential complexity and memory bottlenecks of classical software, the authors position PACOX as a viable path for scaling quantum simulations. The results suggest that such accelerators are essential for supporting larger quantum systems where power and performance are critical constraints. The authors modestly frame this as the first step in dedicated hardware for this specific primitive, highlighting the potential for further scaling on platforms with higher memory bandwidth (e.g., Xilinx Alveo) to support even larger qubit counts.