⚡ electrical engineering

Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

This paper presents a low-jitter, regenerative cross-coupled high-voltage level shifter fabricated in 22-nm FD-SOI technology that generates synchronized dual-range voltage outputs to enable direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, achieving sub-150-fs jitter at 12.2 GHz with ultra-low power consumption.

Original authors: Behdad Jamadi, Meysam Sohani Darban, Jeffrey S. Walling

Published 2026-07-28

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CC BY 4.0

Original authors: Behdad Jamadi, Meysam Sohani Darban, Jeffrey S. Walling

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine the world inside your smartphone as a bustling city where different neighborhoods speak different languages. In the "Low-Power District," the buildings are tiny and efficient, running on a gentle 0.9-volt breeze. But in the "High-Speed Power District," the skyscrapers are massive and need a roaring 1.8-volt wind to function. The problem is that these districts need to talk to each other constantly. If a message from the Low-Power District tries to shout directly at the High-Power District, it's too quiet to be heard. If the High-Power District tries to whisper back, it might accidentally blow a fuse. To fix this, engineers build "level shifters"—tiny translators that take a quiet signal and boost it to a loud one without losing the rhythm or the timing.

But here's the catch: in the high-speed world of modern radio chips, timing is everything. If the translator is even a tiny bit slow, or if the "loud" signal arrives a fraction of a second after the "quiet" one, the whole system stutters. It's like a drummer and a bassist trying to play a song; if the bassist is even slightly out of sync, the music sounds muddy and weak. For years, engineers have struggled to build translators that are both fast enough to keep up with the city's frantic pace and precise enough to keep the rhythm perfect, all while using very little energy. This paper dives into that exact challenge, proposing a new kind of translator that doesn't just speak two languages, but sings in perfect harmony.

The authors of this paper have designed a new "Hybrid Voltage Level Shifter" (HVLS) that acts like a super-efficient, double-talking translator. Instead of just boosting a signal from a low voltage to a high one, this new chip does something clever: it generates two synchronized outputs at the exact same time. One output stays at the original low voltage, and the other jumps up to exactly double that voltage. Think of it as a conductor who, instead of just handing a baton to a louder musician, instantly hands out two batons—one for the quiet section and one for the loud section—ensuring they both start playing at the exact same split second. This is crucial for a specific type of high-speed amplifier (called a cascoded class-D power amplifier) where two transistors must switch on and off in perfect unison. If they are even slightly out of step, the amplifier loses power and efficiency, much like a rowing team where one oar dips a millisecond later than the other.

To prove their idea works, the team built a prototype chip using a very advanced 22-nanometer manufacturing process. They didn't just simulate it on a computer; they actually measured it in the real world. The results were impressive: the chip could handle signals switching at a blistering 12.2 GHz (that's 12.2 billion times per second). At this speed, it consumed only 4.43 microwatts of power per switch and kept the timing jitter (the "wobble" in the rhythm) incredibly low, at less than 150 femtoseconds. To put that in perspective, a femtosecond is to a second what a second is to about 31.7 million years. The chip is so precise that it barely wobbles at all.

The paper also takes a moment to explain why the old ways of doing this didn't work well enough. They looked at three common types of translators used in the past. One type was fast but fought with itself, wasting energy like a car engine revving while in neutral. Another type saved energy but was too slow, like a snail trying to keep up with a race car. A third type tried to be a compromise but ended up being too weak to drive the heavy loads needed for modern amplifiers. The authors argue that none of these old designs could simultaneously be fast, low-power, and perfectly synchronized. Their new hybrid design solves this by using a "regenerative cross-coupled feedback network." Imagine a group of friends passing a ball; if one friend starts running, the others immediately react and speed up to match them, creating a chain reaction that makes the whole group move faster and more smoothly. This is exactly what the chip does with electricity, creating a self-reinforcing loop that snaps the signal into place instantly.

In their tests, the team showed that this new design could operate at speeds up to 19 GHz in simulations, though they measured it at 12.2 GHz to be safe. They also demonstrated that even if the temperature changed or the manufacturing process had tiny variations (which always happens in real life), the chip remained stable and fast. The paper concludes that this new architecture is a strong candidate for the next generation of wireless systems, particularly those operating in the emerging FR3 frequency bands, where speed and synchronization are the keys to unlocking faster data and clearer connections. By solving the timing mismatch problem without needing extra, bulky calibration circuits, this tiny chip could help make future wireless devices more powerful and energy-efficient.

Technical Summary: A High-Speed Differential Hybrid Voltage Level Shifter With Simultaneous Multi-Level Outputs

Problem Statement
Modern mixed-signal and digital radio-frequency (RF) systems, particularly those utilizing switched-capacitor power amplifiers (SCPAs) and digital transmitters, increasingly rely on multi-voltage-domain architectures to enhance efficiency and performance. A critical bottleneck in these systems is the voltage level shifter (VLS), which interfaces low-voltage digital logic ( $V_{DDL}$ ) with high-voltage analog or power stages ( $V_{DDH}$ ).

Conventional VLS topologies—specifically Differential-Cascade Voltage Shifters (DCVS), Current-Mirror Level Shifters (CMLS), and Wilson Current-Mirror Level Shifters (WCMLS)—suffer from inherent trade-offs. DCVS designs often suffer from significant contention currents that degrade switching speed and increase power, especially at low input voltages. CMLS architectures reduce contention but introduce high static power consumption due to continuous current paths. WCMLS designs eliminate static current but suffer from limited drive strength and high propagation delays, making them unsuitable for high-frequency applications.

Furthermore, in cascoded class-D power amplifiers, the upper PMOS and lower NMOS transistors must be driven by signals at different voltage levels ( $V_{DDL}$ and $V_{DDH}$ ) that are perfectly synchronized. Traditional solutions often generate these signals separately or use programmable delay chains to align them. However, such delay chains are sensitive to process, voltage, and temperature (PVT) variations and require complex calibration circuitry. The paper posits that even minor timing mismatches between these drive signals can cause duty-cycle distortion, significantly degrading the output power of the amplifier, particularly as operating frequencies enter the multi-GHz regime.

Methodology and Proposed Architecture
To address these limitations, the authors propose a novel Hybrid Voltage Level Shifter (HVLS) architecture designed for high-speed, low-jitter operation. The core innovation lies in a regenerative cross-coupled feedback network that simultaneously generates two synchronized outputs: one at the nominal supply voltage ( $V_{DDL}$ ) and one at twice that value ( $V_{DDH} = 2V_{DDL}$ ).

The circuit schematic integrates several enhancement techniques:

Regenerative Cross-Coupling: A cross-coupled PMOS pair ( $P5-P6$ ) accelerates output transitions by introducing strong positive feedback.
Contention Mitigation: Diode-connected PMOS devices ( $P3-P4$ ) are placed in series with NMOS devices ( $N5-N6$ ) to mitigate current contention between pull-up and pull-down networks.
Auxiliary Acceleration: The NMOS devices ( $N5-N6$ ) act as cross-coupled transistors with gates tied to the high-voltage outputs, creating an auxiliary current path that further sharpens transitions.
Current Limiting: Transistors $P1$ and $P2$ limit contention current in the outer branches, while their gates are biased at $V_{DDL}$ to prevent gate overstress under high supply voltages.

The authors developed an analytical model to quantify the impact of delay mismatch on the output power of cascoded class-D PAs. This model considers both ideal switching conditions and non-ideal scenarios involving finite rise/fall times and parasitic capacitances. The analysis demonstrates that delay mismatch introduces a time constant during the switching edge, effectively modeling the transition as a combination of ramp and exponential signals, which reduces the fundamental Fourier coefficient of the output waveform and thus the output power.

Key Contributions

Simultaneous Multi-Level Generation: The HVLS generates both the low-voltage ( $V_{DDL}$ ) and high-voltage ( $V_{DDH}$ ) outputs simultaneously and synchronously, eliminating the need for external delay-calibration circuitry in cascoded PA applications.
High-Speed Operation: The architecture is optimized to operate well beyond the multi-GHz barrier, targeting emerging Frequency Range 3 (FR3) band applications.
Low Jitter: The regenerative feedback network is designed to minimize timing uncertainty (jitter), a critical parameter for maintaining spectral purity in digital transmitters.
Analytical Modeling: The paper provides a detailed derivation of output power degradation in cascoded class-D PAs due to delay mismatch, offering a theoretical basis for the necessity of synchronous level shifting.

Experimental Results
A prototype of the HVLS, including an impedance-matching network and a pre-driver for characterization, was fabricated in a 22-nm FD-SOI process technology.

Performance: The circuit was characterized at 12.2 GHz. It achieved an output jitter of less than 150 fs-rms.
Power Efficiency: At 12.2 GHz, the HVLS core dissipates 4.43 µW per switching cycle. The total power consumption of the test circuit (including drivers) is 12.35 µW/cycle.
Area: The total die area is $477 \times 462 \, \mu m^2$ , with the active HVLS core occupying only $3.26 \times 2 \, \mu m^2$ .
Frequency Range: Post-layout simulations indicate the circuit can support frequencies up to approximately 19 GHz.
Comparison: Compared to state-of-the-art level shifters, the proposed design demonstrates superior performance in the high-frequency regime, achieving a Figure-of-Merit (FOM) of 117,278 in RF operating mode, significantly outperforming prior works characterized primarily at MHz frequencies.

Significance and Claims
The paper claims that the proposed HVLS solves two critical problems in high-speed mixed-voltage systems: the generation of synchronized multi-level outputs and the elimination of timing mismatch-induced power degradation in cascoded class-D amplifiers. By removing the need for programmable delay chains, the design simplifies system architecture and improves robustness against PVT variations. The authors assert that this architecture enables the practical implementation of high-speed cascoded class-D topologies, which are essential for next-generation wireless systems and digital RF transmitters. The work is presented as a general solution for high-speed, low-jitter level shifting in advanced CMOS technologies, suitable for applications ranging from digital I/Os to mixed-signal power management.

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