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FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

FusionCell is a novel dual-modality deep learning framework that integrates routed layout geometry and netlist topology via a topology-guided cross-attention mechanism to achieve highly accurate and rapid prediction of standard-cell performance metrics, significantly outperforming existing baselines and traditional simulation methods.

Original authors: Haoyi Zhang, Kairong Guo, Bojie Zhang, Yibo Lin, Runsheng Wang

Published 2026-05-21

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CC BY 4.0

Original authors: Haoyi Zhang, Kairong Guo, Bojie Zhang, Yibo Lin, Runsheng Wang

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to predict how fast a specific type of car engine will run. To do this accurately, you need two things:

The Blueprint (Netlist): This tells you how the parts are connected—where the fuel line goes, which piston connects to which valve, and the electrical logic of the engine.
The Physical Engine (Layout): This is the actual metal and plastic. It tells you how long the pipes are, how thick the wires are, and how close the parts are sitting next to each other.

In the world of computer chips, these "engines" are called Standard Cells. They are the tiny building blocks that make up everything from your phone to your laptop.

The Problem: The Slow Way vs. The Wrong Way

Traditionally, engineers figure out how fast these cells run by running massive, slow computer simulations. It's like building a full-scale physical model of the engine and testing it in a wind tunnel. This is accurate, but it takes days to test just a few variations.

Some faster methods tried to use Artificial Intelligence (AI) to guess the speed.

The "Vision-Only" Mistake: Some AI just looked at a picture of the engine (the layout) without reading the blueprint. It was like trying to guess how fast a car goes just by looking at a photo of the paint job, ignoring the engine size. It missed the critical connections.
The "Blueprint-Only" Mistake: Other AI only read the blueprint (the netlist) and ignored the physical shape. It was like reading a recipe but ignoring whether you are using a tiny pot or a giant one. It missed how the physical size changes the speed.

Both approaches were fast but inaccurate because they ignored half the story.

The Solution: FusionCell

The paper introduces a new AI called FusionCell. Think of FusionCell as a master mechanic who refuses to look at just one thing. It forces the AI to look at the Blueprint and the Physical Engine at the exact same time, but in a very specific way.

Here is how it works, using a simple analogy:

The "Map and Satellite" Analogy
Imagine you have a Satellite Image of a city (the Layout) and a Street Map (the Netlist).

If you just look at the satellite image, you see roads and buildings, but you don't know which road leads to the hospital.
If you just look at the map, you know the hospital is connected to Main Street, but you don't know if Main Street is a narrow alley or a wide highway.

FusionCell's Secret Sauce:
Instead of just gluing the map and the photo together, FusionCell uses the Map as a "Search Query."

It takes the "Map" (the Netlist) and asks: "Where is the connection for the Output Signal?"
It then uses that question to actively scan the Satellite Image (the Layout) to find the exact metal wires and paths that correspond to that signal.
It combines the "where" (from the map) with the "what" (the physical shape of the wires) to calculate the speed.

This is called Topology-Guided Fusion. The electrical connections (the map) guide the AI to look at the specific physical parts (the image) that matter, ignoring the rest of the background noise.

The Results

The researchers tested this on a massive dataset of over 19,500 different chip designs (based on a 7nm process, which is very advanced).

Speed: While traditional methods took days to simulate these chips, FusionCell did it in milliseconds. That is a 10,000x speedup.
Accuracy: It was incredibly precise, with an average error rate of less than 1%.
Ranking: It didn't just guess the numbers; it correctly figured out which chip designs were faster than others, which is crucial for engineers choosing the best parts for a new chip.

Why It Matters

The paper claims that by fusing the "skeleton" (the connections) with the "flesh" (the physical layout) using this smart search method, FusionCell allows engineers to explore millions of design possibilities in the time it used to take to test just a few. It doesn't just make predictions faster; it makes the predictions trustworthy enough to replace the slow, old-school simulations for many tasks.

In short: FusionCell is a super-fast, super-accurate AI mechanic that reads the blueprint and looks at the engine simultaneously to tell you exactly how the car will perform, without needing to build a real prototype first.

Technical Summary: FusionCell

Problem Statement

Standard cells serve as the fundamental building blocks of digital VLSI circuits, where their delay and power characteristics critically determine overall chip performance. Traditional characterization relies on a slow, multi-step pipeline involving Resistance/Capacitance (R/C) extraction from layout geometry followed by exhaustive circuit simulation. This process can take days for a full library, creating a bottleneck for Design Technology Co-Optimization (DTCO) pipelines that require rapid iteration over vast design spaces.

While Machine Learning (ML) approaches have been proposed to accelerate this process, existing methods suffer from significant limitations:

Netlist-only models: Graph Neural Networks (GNNs) and Graph Transformers capture topological connectivity but ignore layout geometry, failing to account for layout-dependent R/C effects.
Layout-only models: Vision-based regressors capture spatial details but lack netlist context, unable to distinguish between electrically active signals and dummy fills or to respect connectivity constraints.
Naive Fusion: Previous attempts to combine these modalities often rely on late fusion or symmetrical concatenation, which fails to establish fine-grained correspondence between specific electrical nodes and their physical geometric realizations.

The core challenge is to jointly represent layout geometry and netlist topology such that models can capture fine-grained spatial details (parasitics) alongside structural connectivity for accurate performance prediction.

Methodology: FusionCell

FusionCell is a dual-modality predictor designed to treat routed layout geometry and netlist topology as mandatory, explicitly fused inputs. The architecture is built on the physical intuition that the netlist defines the "skeleton" (performance envelope) while the layout provides the "flesh" (R/C variations), requiring a topology-guided mechanism to interpret geometry.

1. Layout Representation (DeiT Encoder)

The routed layout is treated as a multi-layer image tensor.

Input: A three-channel tensor representing the primary routing layers (M0, M1, M2). Pixels are populated with normalized Net IDs rather than binary occupancy to preserve semantic connectivity across layers.
Preprocessing: Vertical connectivity (vias) is preserved via inter-layer projection onto adjacent 2D metal planes. Layouts are aligned along their longer dimension to minimize padding artifacts.
Encoding: A Data-Efficient Image Transformer (DeiT) backbone processes the tensor, splitting it into patches and generating a sequence of spatial layout tokens ( $Z_L$ ). This global self-attention mechanism is chosen for its ability to model long-range distributed effects, such as IR drop and cumulative coupling capacitance.

2. Netlist Representation (Graph Transformer)

The netlist is modeled as a heterogeneous graph to capture both local connectivity and global correlations.

Graph Construction: The graph contains two node types: Device Nodes (transistors with attributes like drive strength) and Net Nodes (electrical connections).
Edges: Two edge types are defined:
- Connectivity Edges: Physical wiring between devices and nets.
- Correlation Edges: Links between structurally related nets to capture signal flow and potential interference.
Encoding: A Graph Transformer encoder processes this heterogeneous graph. It employs a structural bias in the attention mechanism to enforce message passing only between connected nodes, ensuring the model respects the underlying circuit topology while capturing global dependencies. This produces graph tokens ( $Z_G$ ).

3. Topology-Guided Multimodal Fusion

The core innovation is an asymmetric cross-attention mechanism where the netlist acts as a structural "map" to query the layout.

Mechanism: Graph tokens ( $Z_G$ ) serve as Queries, while layout tokens ( $Z_L$ ) serve as Keys and Values.
Function: For each electrical node (e.g., an output net), the attention mechanism actively scans the layout to retrieve relevant geometric details (metal tracks, vias).
Inductive Bias: This design enforces that layout features are only considered insofar as they affect specific electrical components, preventing the model from overfitting to background textures or irrelevant silicon areas.
Output: The fused tokens are aggregated via mask-aware pooling and passed to a Multilayer Perceptron (MLP) regression head to predict six metrics: Rise/Fall Delay, Rise/Fall Transition, and Rise/Fall Power.

Key Contributions

FusionCell Framework: A dual-modality predictor that integrates routed layout geometry and netlist topology via a topology-guided cross-attention mechanism, achieving accurate and ranking-stable performance prediction.
Geometry-Preserving Encoding: A representation strategy for routed layouts using DeiT that retains R/C-critical metal and via information across multiple routing layers, enabling fine-grained spatial reasoning.
Topology-Aware Netlist Modeling: A heterogeneous graph representation using Graph Transformers that explicitly captures both device-net connectivity and net-net correlations, providing an electrically meaningful structural representation.
7nm Dataset: The generation of a large-scale dataset based on the ASAP7 PDK containing over 19,500 cells across 149 types, generated via automatic tools, targeting six key delay and power metrics.

Experimental Results

Experiments were conducted on the 7nm ASAP7 benchmark, comparing FusionCell against vision-only, late-fusion, symmetrical-fusion, and state-of-the-art (ProtoCellLayout) baselines.

Regression Accuracy: FusionCell achieved an average Mean Absolute Percentage Error (MAPE) of 0.92% and an $R^2$ of 0.977. This significantly outperformed the best baseline (Symmetrical Fusion, 2.19% MAPE) and the state-of-the-art ProtoCellLayout (4.16% MAPE).
Ranking Consistency: For cell variant ranking (critical for synthesis), FusionCell achieved a Spearman's $\rho$ of 0.86 and Kendall's $\tau$ of 0.76, demonstrating superior ability to distinguish fine-grained structural differences compared to baselines which often failed to rank variants correctly.
Efficiency: FusionCell completed inference for the entire 19.5k cell dataset in approximately 67 seconds on a single GPU. This represents a $10^4\times$ speedup compared to traditional simulation, which required over 5 days to generate the same golden labels.
Ablation Studies: Removing the topology-guided fusion (replacing it with symmetrical fusion) or removing correlation edges from the graph resulted in significant performance degradation, validating the necessity of the directed query mechanism and the inclusion of net-net correlations.

Significance and Impact

The paper claims that FusionCell establishes a generalizable paradigm for multimodal Electronic Design Automation (EDA) by aligning model architecture with the physical hierarchy of design data. By treating the netlist as an active query mechanism for layout geometry, the model mimics the physical R/C extraction process, ensuring that predictions are grounded in electrical connectivity rather than visual texture.

The primary significance lies in enabling rapid design-space exploration. By replacing days of heavy computation with millisecond-level inference, FusionCell allows designers to screen candidates and identify Pareto-optimal cells before running expensive sign-off simulations. This acceleration is crucial for DTCO pipelines and contributes to reducing the energy consumption and carbon footprint of the chip design process. The work positions itself as a step toward democratizing advanced EDA tools by making high-fidelity performance prediction accessible and fast.