Design of An Energy Efficient Toggled MRAM Bit-Cell

Technical Summary: Design of an Energy Efficient Toggled MRAM Bit-Cell

Problem Statement
The paper addresses the limitations of current Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) technologies, specifically the high write current requirements (~100 µA) and lower sense margins that hinder scalability and commercialization. While STT-MRAM offers non-volatility and high endurance, the demand for high write currents constrains transistor scaling. Furthermore, conventional Magnetic Tunnel Junctions (MTJs) often rely on in-plane magnetic anisotropy (IMA), which lacks the stability and efficiency required for next-generation nanoelectronic devices. The authors identify a need for a memory architecture that minimizes switching error rates, reduces power consumption, and improves switching speed without relying solely on high current densities.

Methodology
The authors propose a design for a Toggle Spin Torque Magnetic Random-Access Memory (TST-MRAM) bit-cell that leverages the Voltage-Controlled Magnetic Anisotropy (VCMA) effect. The study employs micromagnetic simulations using the NIST-Simulmag toolkit to model the magnetization precession and switching behavior of the proposed cell.

Key methodological elements include:

• Material Interfaces: The design utilizes specific material interfaces, notably Heavy Metal (HM) / Cobalt-Iron-Boron (CoFeB) / Non-Magnetic (NM) / Magnesium Oxide (MgO) structures (e.g., Ta/CoFeB/MgO and W/CoFeB/MgO). These interfaces are engineered to induce strong interfacial Perpendicular Magnetic Anisotropy (iPMA).
• Physical Modeling: The simulation is based on the Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation, which governs the dynamics of magnetization under the influence of effective magnetic fields, spin-transfer torque, and damping.
• Simulation Parameters: The study models various parameters including magnetization factors, resistivity, anisotropy constants, and geometric dimensions (e.g., free layer thickness of 1.49 nm for CoFeB and 1.4 nm for MgO). The simulations track the evolution of magnetization in x, y, and z directions over dynamic time intervals to evaluate switching performance.

Key Contributions
The paper presents three primary contributions to the field of spintronic memory design:

1. VCMA-Based TST-MRAM Design: The authors propose a toggled MRAM bit-cell design that utilizes the VCMA effect to facilitate fast switching and extremely low switching power. This design achieves a low damping ratio, high anisotropy coefficient, and large magnetic polar orientation in the z-direction.
2. Azimuthal Orientation Consideration: Unlike classical magnetic memory designs, this work explicitly considers the azimuthal orientation in a focal plane to enhance the stability of the bit-cell.
3. Micromagnetic Insight: The study provides a detailed theoretical and graphical analysis of micromagnetic effects, offering deep insights into critical parameters such as magnetization factors, polar orientation, and azimuthal orientation required for novel toggled MRAM bit-cell design.

Results
The micromagnetic simulations yielded the following quantitative results for the proposed VCMA-assisted TST-MRAM bit-cell:

• Switching Performance: The design demonstrates significant improvements in read and write access times compared to existing technologies. The paper reports enhancements of 216% and 568% in read/write times compared to STT-MRAM, and 113% and 366% compared to Spin-Orbit Torque (SOT)-MRAM.
• Magnetization and Anisotropy: The optimized design achieved a maximum principal magnetization of 950 kA/m in the ferromagnetic layer. The anisotropic coefficient was found to be 21 times greater than that of standard STT-MRAM cells and 20 times greater than SOT-MRAM cells.
• Damping and Polarization: The damping ratio showed a significant increase (reported as 403% and 416% relative to in-plane and interfacial perpendicular MTJ configurations, respectively), while the polarization factor was reduced by 22% and 26% compared to STT-MRAM and SOT-MRAM, respectively.
• Specific Parameters: The final design parameters included a channel length of 70 nm, a magnetic polar orientation of 70.9°, a magnetic anisotropy field of 1884.9 kA/m, and a damping constant of 0.0035. The total dynamic time for the toggle-based memory cell development was recorded at approximately 2.02–2.04 µs.

Significance and Claims
The paper claims that the proposed TST-MRAM bit-cell design offers a viable path toward ultra-low power and sub-nanosecond switching regimes for non-volatile memory. By integrating the VCMA effect with specific HM/CoFeB/MgO interfaces, the design successfully minimizes switching error rates and power requirements while maintaining high thermal stability (targeting a stability factor of 75 for 128 GB chips).

The authors assert that this bit-cell is suitable for applications in aerospace, memory storage, quantum computing, and space applications. They conclude that the design outperforms state-of-the-art alternatives in terms of switching speed, energy efficiency, and stability, positioning it as a strong candidate for future spin-based computing units. The work suggests that further advancements in spin-based memory could be achieved by exploring domain wall logic, though this is noted as a future direction rather than a current result.