⚡ electrical engineering

Compact Zigzag Hexagonal On-Chip Inductor for Area-Efficient Millimeter-Wave RFICs

This paper presents a compact zigzag hexagonal on-chip inductor designed in a 45 nm CMOS process that achieves a 17% reduction in silicon area compared to conventional octagonal spirals while maintaining high inductance density and quality factor, as validated by a 31 GHz low-noise amplifier achieving 24.2 dB gain and 2.64 dB noise figure.

Original authors: Naveen Manchala, Bheema Rao Nistala

Published 2026-08-26

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CC BY 4.0

Original authors: Naveen Manchala, Bheema Rao Nistala

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Modern wireless devices, from smartphones to satellite links, rely on a hidden layer of tiny electronic components to catch, amplify, and process invisible radio waves. Among these components, the inductor is a fundamental building block, acting as a magnetic storage unit that helps tune circuits to specific frequencies. In the world of silicon chips, these inductors are flat, spiral-shaped coils etched directly onto the surface. While essential, they have a stubborn drawback: they are bulky. To get the right amount of magnetic storage, engineers often have to draw large spirals that consume valuable space on the chip. As devices shrink and demand faster data speeds, this wasted space becomes a critical bottleneck, forcing designers to choose between a compact chip and a high-performing one.

Researchers at the National Institute of Technology Warangal in India have tackled this spatial dilemma by redesigning the shape of the on-chip inductor. In a study focused on millimeter-wave technology—the high-frequency band used for next-generation 5G and beyond—they proposed a new geometry that packs more magnetic power into a smaller footprint. Instead of the standard, smooth octagonal spirals commonly found in chip design kits, the team introduced a "zigzag" pattern within a hexagonal shape. Imagine a highway where the lanes are not straight but weave back and forth in a tight, efficient pattern; this allows a longer road to fit into the same city block. By weaving the conductor path in this specific zigzag manner, the researchers increased the length of the metal wire and the magnetic interaction between its parts without expanding the overall size of the component.

The team created a digital model of this new inductor using a 45-nanometer manufacturing process, a standard for modern high-speed chips. They did not just draw the shape; they built a flexible, programmable version of it that could be automatically adjusted for different design needs. Through detailed computer simulations that mimic the behavior of electromagnetic waves, they tested how well this new shape performed at 30 gigahertz, a frequency typical for advanced wireless communication. The results were precise: the new inductor stored 162.8 picohenries of inductance and maintained a quality factor of 10.08, a measure of how efficiently it stores energy without losing it to heat. Crucially, when compared to a traditional octagonal spiral designed with the exact same rules and materials, this new zigzag hexagonal version occupied roughly 17 percent less silicon area while delivering nearly identical electrical performance.

To prove that this compact shape works in a real circuit, the researchers embedded it into a low-noise amplifier, a device designed to boost weak radio signals without adding static. They replaced the standard, larger inductors in a 31-gigahertz amplifier design with their new compact versions. The simulation showed that the amplifier continued to function perfectly, delivering a signal gain of 24.2 decibels and a noise figure of 2.64 decibels, which indicates very little signal distortion. The most striking outcome was the physical footprint of the entire circuit. By swapping in the smaller inductors during the post-layout implementation, the total layout area of the amplifier shrank by 35.2 percent. This reduction was achieved without changing the amplifier's architecture or its active components, demonstrating that the gain in space came entirely from the smarter arrangement of the passive inductor.

The study confirms that by altering the path of the current to include these zigzag segments, engineers can significantly improve how densely they pack inductors onto a chip. This approach offers a practical solution for the future of highly integrated radio-frequency circuits, where every square micrometer of silicon counts. The researchers validated their findings through rigorous electromagnetic modeling and circuit-level testing, showing that the proposed geometry is a viable, area-efficient alternative to conventional designs. As wireless technology pushes toward higher frequencies and smaller devices, such innovations in the shape of basic components will be essential for fitting more capability into less space.

Technical Summary: Compact Zigzag Hexagonal On-Chip Inductor for Area-Efficient Millimeter-Wave RFICs

Problem Statement
The increasing integration density of millimeter-wave radio-frequency integrated circuits (RFICs) has made silicon area a primary design constraint in modern CMOS radio-frequency front-end (RFFE) systems. Passive on-chip inductors, essential for components such as low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), and impedance matching networks, occupy a significant portion of the chip area. Their electrical performance is often limited by conductor resistance, substrate losses, and parasitic capacitances. While commercial Process Design Kits (PDKs) typically provide octagonal spiral inductors as a standard compromise between performance and fabrication reliability, these general-purpose components are often not area-efficient for application-specific millimeter-wave circuits where multiple inductors must be integrated within a limited footprint. Existing approaches to improve performance, such as multilayer 3D structures or modified planar geometries (e.g., fractal or V-shaped), often introduce additional parasitic effects or fail to provide compact replacements for standard PDK inductors without compromising high-frequency performance.

Methodology
To address these limitations, the authors propose a compact zigzag hexagonal on-chip inductor designed for 45 nm CMOS technology. The core methodology involves:

Geometric Innovation: The proposed geometry introduces zigzag conductor segments within a hexagonal spiral. Unlike conventional spirals where the conductor follows straight edges between vertices, this design utilizes inclined zigzag segments. This configuration increases the effective current path length and magnetic flux linkage within nearly the same projected area, thereby enhancing inductance density without increasing the overall footprint.
Parameterized Cell (PCell) Implementation: The inductor is implemented as a PCell using the SKILL language within the Cadence Virtuoso environment. This allows the geometry to be regenerated automatically based on design parameters (conductor width, spacing, number of turns, metal layer), ensuring compatibility with standard CMOS design flows and facilitating systematic evaluation.
Analytical Modeling: A segment-wise semi-analytical formulation was developed to model the inductance. Unlike equivalent-dimension approaches, this method decomposes the conductor path into $N_s$ straight segments, calculating self-inductance using finite-conductor expressions (Grover) and mutual inductance using the Neumann formulation. This approach explicitly accounts for the coordinates and orientations of the inclined zigzag sections.
Electromagnetic Simulation: Full-wave electromagnetic simulations were conducted using the EMX solver to characterize the inductor's frequency-dependent behavior, including skin effect, proximity effect, and substrate losses.
Circuit-Level Validation: The proposed inductor was integrated into a two-stage, 31 GHz narrowband Low-Noise Amplifier (LNA). The LNA design remained unchanged from a standard topology (using current-reuse common-gate input and common-source gain stages), with the proposed inductors serving as direct replacements for standard PDK octagonal inductors to isolate the impact of the geometry on circuit performance.

Key Contributions

Novel Geometry: Introduction of a zigzag hexagonal spiral topology that extends the effective current path to improve inductance density.
Design Automation: Development of a parameterized cell (PCell) framework that enables flexible generation of the zigzag geometry while adhering to PDK constraints.
Analytical Framework: A segment-wise inductance calculation method that accurately models the unique spatial arrangement of inclined conductor segments.
Area Efficiency: Demonstration of a significant reduction in silicon area compared to conventional octagonal spirals and standard PDK inductors while maintaining or improving RF performance.

Results
The proposed inductor was characterized and validated through the following results:

Inductor Performance: At 30 GHz, the proposed inductor achieves an inductance of 162.8 pH with a quality factor (Q) of 10.08. The maximum Q reaches 25.31 at 113.4 GHz, with a self-resonant frequency (SRF) of 209.9 GHz.
Area Comparison: Compared to an equivalent octagonal spiral designed under identical technology constraints (same conductor width, spacing, and turns), the proposed zigzag hexagonal geometry occupies approximately 17% less silicon area (26 µm × 20.5 µm vs. 23 µm × 27 µm).
PDK Comparison: When compared to standard 45 nm CMOS PDK inductors used in the LNA, the proposed inductors demonstrated a minimum area reduction of 10.9% and a quality factor improvement of over 21% for identical inductance values.
LNA Validation: The 31 GHz LNA incorporating the proposed inductors achieved a post-layout gain of 24.2 dB, a noise figure (NF) of 2.64 dB, and an input return loss (S11) of 19.7 dB at 31.2 GHz.
System-Level Impact: Replacing standard PDK inductors with the proposed compact geometry in the LNA reduced the total layout area by 35.2% (from 0.01674 mm² to 0.01084 mm²) without altering the circuit topology or degrading RF performance.

Significance
The paper claims that the proposed zigzag hexagonal geometry provides a compact and effective solution for highly integrated millimeter-wave CMOS RFICs. By improving inductance density through geometric optimization rather than complex multilayer structures, the design offers a practical alternative to conventional PDK inductors. The results demonstrate that this approach allows for significant area reduction in RFIC layouts while preserving, and in some cases enhancing, critical RF performance metrics such as gain, noise figure, and quality factor. The authors position this work as a promising candidate for compact 5G front-end designs where silicon area efficiency is paramount.

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