⚡ electrical engineering

An Ultra-Compact, BRAM-Free Streaming 2D Convolution Accelerator on Low-Power FPGAs

This paper presents an ultra-compact, BRAM-free streaming 2D convolution accelerator for low-power FPGAs that utilizes LUT-based shift registers and a pipelined MAC datapath to achieve high throughput and minimal resource usage while maintaining bit-exact accuracy on a Xilinx Zynq-7020 SoC.

Original authors: Amir Atef, Yahia Sameh

Published 2026-10-14

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Amir Atef, Yahia Sameh

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the world of modern technology, there is a constant push to make smart devices smaller, cheaper, and capable of running on tiny batteries. This drive has given rise to "edge computing," where complex tasks like recognizing faces or detecting objects happen directly on a camera or a sensor, rather than sending data back to a massive cloud server. The mathematical engine behind this vision is a process called convolution, which acts like a filter sliding over an image to find specific patterns, such as the sharp edge of a building or the curve of a face. To do this, the device must look at a small group of pixels at once, multiply them by specific numbers, and add the results together. While powerful computers in data centers handle this easily, doing it on a small, low-power chip is difficult because the chip has very limited memory and energy. It cannot afford to store the entire image to look back at it, nor can it waste power waiting for data to arrive.

Researchers at Ain Shams University have designed a new hardware accelerator that solves these problems for small, low-power chips found in devices like drones or wearable sensors. They created a specialized circuit that can process a stream of image data as it arrives, one pixel at a time, without ever needing to store the whole picture in memory. The team built this system on a type of reconfigurable chip called an FPGA, specifically targeting a model known as the Zynq-7020, which is common in embedded electronics. Their goal was to strip away all the heavy, power-hungry memory components usually required for this task and replace them with a much lighter, more efficient structure that fits entirely within the chip's basic logic blocks.

The core of their innovation is a method of handling the image data that avoids the need for large, dedicated memory banks. Typically, to analyze a small square of an image, a computer needs to remember the current row of pixels and the two rows that came just before it. Standard designs use large blocks of memory to hold these rows, which consumes valuable space and energy. The researchers instead built a system that uses tiny, flexible storage units found inside the chip's logic fabric. These units act like a moving conveyor belt, holding just enough data to reconstruct the necessary three-by-three square of pixels as the image stream flows past. By using these small, distributed storage elements instead of large memory blocks, they eliminated the need for any dedicated memory tiles, freeing up space for other tasks and drastically reducing the power required to run the system.

The accelerator processes the image data at a steady pace, accepting one pixel every clock cycle. As the pixels flow in, the system instantly forms the required three-by-three neighborhood, multiplies each pixel by its corresponding weight, and adds the results together. To ensure the math remains accurate and does not produce errors due to numbers getting too large, the design uses a specific, mathematically proven size for its internal calculation registers. This guarantees that the sum of the nine multiplied values will never overflow or wrap around incorrectly, a common problem in fixed-size digital systems. Once the calculation is complete, the result is carefully adjusted to fit within a standard range, and an optional step can be applied to remove any negative values, mimicking a common step used in artificial intelligence networks.

The team tested their design rigorously, running it through simulations and comparing the results against a trusted software model. They verified that the hardware produced the exact same output as the software for every single pixel in test images, including complex natural photographs and geometric patterns. When they built the design on the target chip, the results showed that the system consumed almost no memory resources, using zero dedicated memory blocks. It occupied less than half a percent of the chip's total logic capacity and used only a tiny fraction of its specialized math processors. The system ran at a speed of 100 million cycles per second, processing a full frame of a 32-by-32 pixel image in just over ten microseconds.

Power consumption was another major success. The active part of the chip that performs the calculations used only nine milliwatts of power, which is less than the energy required to light a tiny LED. While the total power measured included the energy needed to send signals out of the chip to external pins, the researchers noted that in a real device where the chip talks to other parts internally, this external power cost would disappear, leaving the calculation core to run on less than ten milliwatts. This level of efficiency makes it possible to run advanced vision tasks on devices that are powered by small batteries or even energy harvesting, without the need for large cooling systems or heavy power supplies.

The design is not without its limits. It is currently built specifically for processing single-channel images, such as black-and-white photos, and is optimized for a three-by-three pattern size. Changing the pattern size or handling color images would require rebuilding the circuit. Additionally, the system expects a continuous stream of data and does not have a mechanism to pause and wait if the data source stops. However, for its intended purpose of handling small, fast-moving image patches on low-power hardware, the researchers demonstrated that their approach is a highly efficient solution. By proving that complex image analysis can be done with almost no memory and minimal power, this work opens the door for a new generation of smart, self-contained sensors that can see and understand the world without needing a connection to the cloud.

Technical Summary: An Ultra-Compact, BRAM-Free Streaming 2D Convolution Accelerator on Low-Power FPGAs

Problem Statement

Two-dimensional (2D) spatial convolution is the primary computational workload for edge computer vision and deep learning inference. However, implementing these operations on resource-constrained embedded platforms presents two critical engineering challenges:

Memory Bandwidth and Buffering Bottlenecks: Conventional approaches often buffer full video frames in external DRAM or on-chip Block RAM (BRAM). For raster-scan image sensors, accessing the vertical spatial neighborhood required for a $3 \times 3$ kernel (three adjacent rows) incurs prohibitive memory footprints, high latency, and excessive dynamic power dissipation.
Arithmetic Precision and Overflow: Fixed-point quantized CNN layers (typically 8-bit integers) require careful management of intermediate accumulator growth. Without precise word-length derivation and saturation policies, intermediate overflows can cause wrap-around artifacts (e.g., bright positive activations wrapping to negative values), destabilizing downstream vision models.

Methodology

The authors propose an ultra-compact, streaming hardware accelerator tailored for single-channel image streams on low-power Field-Programmable Gate Arrays (FPGAs). The architecture is implemented in synthesizable Verilog and targets the Xilinx Zynq-7020 SoC.

Core Architectural Innovations

BRAM-Free Streaming Line Buffers: Instead of using dedicated BRAM tiles, the design reconstructs $3 \times 3$ spatial neighborhoods on the fly using dual chained shift-register line buffers. These buffers are mapped entirely onto Look-Up Table (LUT)-based shift-register primitives (SRLC32E). This approach stores only two scanlines ( $2W$ pixels) of data, eliminating BRAM utilization entirely while maintaining single-cycle throughput.
Mathematically Exact Accumulation: The datapath utilizes a 20-bit internal accumulator. The authors provide a formal derivation proving that for 8-bit unsigned inputs ( $[0, 255]$ ) and 8-bit signed weights ( $[-128, 127]$ ), a 20-bit width guarantees zero intermediate overflow across all valid combinations.
Pipelined MAC Datapath: The arithmetic core features a three-stage pipeline:
1. Stage 1: Nine parallel DSP48E1 multipliers compute products simultaneously. Input pixels are zero-extended to prevent signed interpretation errors.
2. Stage 2: A balanced adder tree sums the nine 16-bit products into the 20-bit accumulator.
3. Stage 3: Monotonic 16-bit saturation clamping prevents wrap-around artifacts, followed by an optional Rectified Linear Unit (ReLU) activation.
Deterministic Control: A three-state Moore Finite State Machine (FSM) orchestrates control flow. It employs input stream gating and output-sample drain accounting to ensure complete pipeline flushing without stall overhead, achieving a deterministic initial latency of $2W + 7$ cycles.

Key Contributions

The paper identifies five primary contributions:

BRAM-Free Microarchitecture: A streaming window generator that maps dual line buffers to 16 LUT-based shift registers, freeing scarce BRAM blocks for other neural network parameters.
Formal Dynamic Range Derivation: A mathematical proof demonstrating that a 20-bit accumulator prevents overflow, coupled with a saturation policy that preserves gradient monotonicity.
Zero-Stall Pipeline Control: A control FSM that ensures complete pipeline drains without bubble-insertion stalls, providing a precise latency formula ( $L = 2W + 7$ ).
Rigorous Multi-Tier Verification: Exhaustive testing including unit-level arithmetic stress tests, geometric verification on non-square images ( $64 \times 32$ ), and system-level bit-exact co-simulation against a Python/NumPy golden model on natural photography.
Comprehensive Hardware Characterization: Detailed post-synthesis results on a Xilinx Zynq-7020, including critical-path analysis, power dissipation profiles, and an architectural trade-off analysis between shift registers and BRAMs.

Experimental Results

The accelerator was synthesized and implemented on a Xilinx Zynq-7020 (xc7z020clg400-1) under a 100 MHz clock constraint.

Resource Utilization: The design is ultra-compact, utilizing only 231 Slice LUTs (0.43%), 417 Flip-Flops (0.39%), and 9 DSP48E1 slices (4.09%). Crucially, it reports 0 Block RAM usage.
Timing Performance: The design meets timing with a Worst Negative Slack (WNS) of +3.724 ns, yielding an estimated maximum frequency ( $f_{max}$ ) of 159.3 MHz.
Power Consumption: The active compute power is extremely low at 9 mW. The total on-chip power dissipation is 159 mW, with the majority (83%) attributed to external I/O pad drivers; the core computational fabric consumes only 9 mW.
Throughput and Latency:
- Latency: 71 cycles (710 ns) for a $32 \times 32$ frame.
- Throughput: Sustains 1 output pixel per clock cycle (100 Mpixel/s, 900 MMAC/s).
- Accuracy: Achieved 100% bit-exact equivalence (900/900 samples) against the software golden model on natural photography and 1860-window geometric matches on non-square images.
Efficiency: The authors calculate a Figure of Merit (FOM) of $9.24 \times 10^{-3}$ (peak) and $8.09 \times 10^{-3}$ (average), normalized by power and resource footprint.

Significance and Claims

The paper positions this work as a solution for localized edge vision windows, patch processing, and compact feature maps where memory resources are scarce. The authors claim that by eliminating BRAM dependency and utilizing LUT-based shift registers, the architecture resolves the memory under-utilization inefficiency common in standard line-buffer implementations for small image widths.

The significance lies in the ability to perform high-throughput, mathematically exact 2D convolutions on low-power FPGAs with minimal silicon footprint and power consumption. The design is specifically optimized for scenarios where the image scanline width is small (e.g., $W=32$ ), making it ideal for streaming edge sensors without the need for external DDR memory or large on-chip frame buffers. The authors note that while the current design is specialized for $3 \times 3$ kernels and single-channel streams, it provides a foundational, ultra-compact IP core for edge AI inference.