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A High-Throughput DSP-Free PRNG for FPGA based on Xoshiro128** and Integer Chaotic Mixing

This paper presents a resource-efficient, DSP-free, and fully pipelined hybrid PRNG for the Xilinx Zynq-7000 platform that combines Xoshiro128**, Weyl sequences, and an integer Tent map to achieve high throughput (5.82 Gbps) and pass rigorous statistical tests while maintaining a small footprint suitable for embedded applications.

Original authors: Milad Mohammadian, Bahadin Azizinasab, Abobakr Mohammadian, Mahrokh G. Shayesteh, Mohammad Saeed khayati, Sheida Mohammadpour, Mosleh yousefi

Published 2026-11-09
📖 5 min read🧠 Deep dive

Original authors: Milad Mohammadian, Bahadin Azizinasab, Abobakr Mohammadian, Mahrokh G. Shayesteh, Mohammad Saeed khayati, Sheida Mohammadpour, Mosleh yousefi

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the digital world, many systems rely on sequences of numbers that look completely random to function correctly. These sequences are essential for securing communications, simulating complex physical systems, and running cryptographic protocols. However, true randomness is difficult to generate with a machine, so engineers use algorithms to create "pseudo-random" numbers. These are deterministic sequences that appear random to an observer but are actually produced by a specific set of rules starting from an initial seed. The challenge for hardware designers is to create these sequences quickly and efficiently without consuming too much power or taking up too much space on a computer chip. When these generators are built into specialized chips called FPGAs, which are reconfigurable hardware often used in embedded systems, the goal is to achieve high speed while keeping the design small and energy-efficient, avoiding the use of expensive, power-hungry components that are typically reserved for heavy mathematical calculations.

A team of researchers from universities in Iran has developed a new way to build such a generator that runs on an FPGA. Their work focuses on creating a device that produces a massive stream of random-looking numbers without using the standard high-performance math units found on most chips. Instead of relying on these specialized components, which are often limited in number and consume significant power, the team designed a system that uses only basic logic gates and standard memory registers. The result is a generator that can produce data at a rate of 5.82 gigabits per second, a speed that rivals much more complex designs, while using a very small amount of the chip's resources and consuming minimal power.

The core of this new design is a hybrid approach that combines three different methods of mixing numbers. The primary engine is a well-known algorithm called Xoshiro128**, which acts as the main source of the sequence. This engine is efficient and has a very long cycle before it repeats, but it has a predictable mathematical structure that could be exploited by a skilled attacker. To fix this, the researchers added two extra layers of mixing. The first layer uses a simple additive process that shifts values in a way that creates a different kind of pattern. The second layer uses a "tent" map, a method that stretches and folds the numbers, similar to how a baker might fold dough, though in this case, the folding happens through simple integer math rather than physical manipulation. These layers are designed to work together to break up the predictable patterns of the main engine, making the final output much harder to reverse-engineer.

The researchers built this system using a high-level synthesis tool, which automatically translates a software description of the logic into the physical layout of the chip. They tested the design on a specific type of chip known as the Xilinx Zynq-7000. The implementation was successful in every metric that mattered for embedded applications. The final design occupied only 934 small logic blocks on the chip and used 1,071 registers, a very compact footprint. Crucially, it used zero of the specialized digital signal processing slices and zero blocks of dedicated memory, proving that high-speed random number generation is possible without these heavy resources. The system ran at a frequency of 181.82 megahertz, delivering the high throughput mentioned earlier. In terms of power, the chip consumed only 29 milliwatts of dynamic power during operation, a figure that represents a lower bound estimate and suggests the design is extremely energy-efficient.

To ensure the numbers produced were truly random enough for serious use, the team subjected the output to a battery of rigorous statistical tests. These tests, which include standard suites used by government agencies and independent researchers, check for patterns, biases, and correlations that would indicate a lack of randomness. The generator passed every single test, including the most demanding ones that look for subtle flaws in the sequence. The researchers also analyzed how sensitive the system was to changes in its starting conditions. They found that changing even a single bit in the initial setup caused the output to diverge completely, a property known as sensitivity to initial conditions. This ensures that two devices starting with slightly different seeds will produce entirely different sequences, which is vital for security.

The study also included a detailed breakdown of what each part of the system contributed. The researchers found that the main Xoshiro128** engine was already statistically strong enough to pass the tests on its own. The added layers did not improve the statistical quality of the numbers, but they did something else important: they removed the linear mathematical structure that made the main engine predictable. By adding these layers, the researchers made it significantly harder for an attacker to figure out the internal state of the generator just by looking at the output. While the main engine alone could be reverse-engineered relatively quickly, the full hybrid system requires a much more complex and time-consuming effort to break, effectively securing the generator against certain types of attacks without sacrificing speed or efficiency.

This work suggests that it is possible to build high-performance random number generators for resource-constrained environments without relying on heavy hardware components. The design offers a practical trade-off, balancing speed, resource usage, and security. While the researchers note that the mathematical steps used in the folding layer are not algebraically complex, their combination with the other layers creates a robust system. The findings indicate that this approach is well-suited for embedded systems where space and power are at a premium, providing a reliable source of randomness that can be integrated into a wide range of devices. The researchers have made their code and data available for others to verify and build upon, ensuring that the results can be reproduced and the design can be adapted for future needs.

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