A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

1. Problem Statement

In Quantum Key Distribution (QKD) systems, Time-to-Digital Converters (TDCs) are critical for timestamping photon arrivals to identify coincident events. While Field-Programmable Gate Array (FPGA)-based TDCs offer cost-effective and flexible solutions, they suffer from intrinsic nonlinearity caused by the physical imperfections of the FPGA delay fabric (e.g., carry-chain distortion).

• Current Limitation: Existing research typically treats TDC nonlinearity as a calibration issue, relying on post-processing statistical corrections (e.g., Look-Up Tables) to fix timing errors.
• The Gap: In QKD, raw nonlinearity is a security-relevant parameter, not just a performance metric. Deterministic non-uniformities (such as ultra-wide or zero-width bins) force the system to widen the "coincidence window" to avoid rejecting valid photon events.
• Consequence: A wider coincidence window increases the rate of accidental coincidences (noise), which directly elevates the Quantum Bit Error Rate (QBER). A higher QBER reduces the secure key rate and the overall security margin of the QKD system. Previous works have largely ignored the direct impact of raw, uncalibrated nonlinearity on security metrics.

2. Methodology

The authors propose a "security-aware" approach that combines a conservative analytical model with hardware-level mitigation strategies.

A. Analytical Modeling

The paper derives a system-level model linking TDC nonlinearity to QKD metrics:

1. Hybrid Timing Model: The model separates timing errors into random jitter (stochastic) and deterministic nonlinearity (peak-to-peak Integral Nonlinearity, $W_{INL,pp}$).
2. Coincidence Window Expansion: The effective coincidence window ($\Delta t_{eff}$) is defined as the nominal window plus the peak-to-peak INL ($\Delta t_{eff} = \Delta t_0 + W_{INL,pp}$). This assumes a worst-case scenario where the full raw distortion must be tolerated.
3. QBER Formulation: The model calculates the incremental QBER ($\Delta QBER_{TDC}$) by accounting for how the expanded window increases accidental coincidence rates ($C_{acc}$) relative to true coincidences.

B. Hardware Mitigation Strategies

Instead of relying solely on post-calibration, the authors propose fabric-level optimizations to reshape the delay line physically:

1. LUT-Assisted Delay Shaping:
   • Introduces Look-Up Table (LUT) configured inverters and manual routing selection between the carry chain and sampling flip-flops (DFFs).
   • Goal: To inject controlled delays to "fill" near-zero bins and smooth out ultra-wide bins, effectively redistributing bin widths before the transfer function is extracted.
2. Placement Constraints:
   • Applies manual placement constraints (LOC) to keep the entire delay chain within a single clock region to avoid Clock Region Crossing (CRC) skew.
   • Ensures DFFs are strictly aligned with their corresponding delay chains to minimize routing-dependent irregularities.

C. Experimental Setup

• Platform: Low-cost Zynq-7000 FPGA (Zynq-7020).
• Test Subjects: Two open-source TDC designs were reproduced and optimized:
  • TDC-1: Long-chain design (996 bins, 100 MHz) spanning a large portion of the fabric.
  • TDC-2: Short-chain design (4 $\times$ 96 bins, 260 MHz) for complementary analysis.
• Evaluation: The study uses measured raw nonlinearity data (without statistical calibration) and feeds it into the analytical model to simulate QBER impacts under representative QKD parameters (using SPAD and SNSPD detectors).

3. Key Contributions

1. Security-Aware Analytical Model: A conservative framework that explicitly links raw TDC nonlinearity (INL) to the expansion of the coincidence window and the resulting degradation of QBER and secret fraction.
2. Fabric-Level Mitigation: A novel hardware strategy using LUT-based delay injection and placement constraints to physically correct bin-width irregularities, reducing the root cause of nonlinearity rather than just masking it.
3. Quantified Security Impact: Demonstration that raw nonlinearity significantly affects the estimated secret fraction in QKD, even when the absolute QBER reduction appears small.

4. Results

The study compared non-optimized (raw) designs against the optimized versions:

• Nonlinearity Reduction:
  • TDC-1 (Long-chain): Reduced peak-to-peak INL by 21% (from 280.2 ps to 215.7 ps) and Differential Nonlinearity (DNL) range by 60%. Single-shot precision ($\sigma_{TDC}$) improved by 25%.
  • TDC-2 (Short-chain): Reduced INL by 14% and DNL by 16%.
• QBER Improvement:
  • TDC-1: Reduced TDC-induced incremental QBER from 1.71% to 1.32% (relative reduction of ~22.8%).
  • TDC-2: Reduced incremental QBER from 0.95% to 0.81% (relative reduction of ~14.7%).
• Secret Fraction Gain:
  • Even small QBER reductions translate to significant gains in the secure key rate.
  • For TDC-2, a tiny 0.14% QBER reduction improved the estimated secret fraction by 3.7%.
  • For TDC-1, the improvement in secret fraction reached 14.2%.

5. Significance

This paper shifts the paradigm for FPGA-based TDCs in QKD from a purely "calibration-centric" view to a "security-aware hardware design" perspective.

• Physical Security: It demonstrates that raw hardware imperfections directly compromise the security margin (QBER floor) of QKD systems.
• Design Implication: Relying solely on post-processing calibration is insufficient for high-security applications; physical delay-line shaping is necessary to minimize worst-case timing distortions.
• Practicality: The proposed methods are implementable on low-cost, widely available FPGAs (Zynq-7000), making high-security QKD more accessible for edge deployments and the "Quantum Internet of Things."

In conclusion, the authors prove that addressing raw nonlinearity at the hardware level yields measurable improvements in QKD security metrics, validating the need for explicit nonlinearity consideration in timing-sensitive quantum systems.