🤖 machine learning

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

PPAPlace introduces a differentiable, timing-driven surrogate model trained on post-global-routing labels that leverages dual-stream graph and spatial attention to predict and optimize post-route power, performance, and area (PPA) metrics, significantly improving worst negative slack and total negative slack over hierarchical baselines without requiring test-circuit retraining.

Original authors: Ruogu Chen, Jie Han

Published 2026-08-17

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CC BY 4.0

Original authors: Ruogu Chen, Jie Han

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are an architect trying to build the most efficient city possible, but instead of skyscrapers and parks, you are arranging tiny electronic components on a microscopic silicon chip. This is the world of chip placement, a critical step in making the computers and phones we use every day. The goal is to arrange these components so that electricity can travel between them as quickly as possible, using the least amount of energy and space. If the arrangement is messy, the signals get stuck in traffic, the chip runs hot, and the battery dies fast. For decades, engineers have used a simple rule of thumb to organize these chips: they try to minimize the total length of the wires connecting the parts. It's like trying to lay out a city by just making sure the roads are as short as possible. But here's the twist: just because the roads are short doesn't mean the traffic flows smoothly. Sometimes, a short road leads to a dead end or a bottleneck, causing the whole city to gridlock. This paper explores why that old rule of thumb often fails and introduces a new, smarter way to design these microscopic cities.

The researchers, Ruogu Chen and Jie Han, discovered that the old method of just counting wire lengths is actually a terrible predictor of how well a chip will perform in the real world. They found that optimizing for short wires often leads to chips that are slower and less efficient than those designed with the standard industry baseline, Hier-RTLMP, and other prior AI methods. To fix this, they built a "crystal ball" for chip designers. This crystal ball is a special computer program that can look at a chip layout and predict exactly how fast it will run and how much power it will use, even before the chip is fully built. Unlike previous attempts that only looked at the big, important buildings (called macros) and guessed based on early, rough drafts, this new tool looks at the entire city, including the tiny houses (standard cells) and the traffic patterns on the roads.

The secret sauce of their new tool, called PPAPlace, is that it learns from the "final exam" results of chip designs. Instead of guessing based on early sketches, it studies the results after the chip has gone through a full simulation of traffic and power usage. This allows it to understand the true bottlenecks that cause slowdowns. Once the tool is trained, it doesn't just give a score; it gives a map. It tells the designer exactly which tiny component to move, and in which direction, to make the chip run faster. Think of it like a GPS that doesn't just tell you the shortest route, but actively steers your car around traffic jams in real-time.

The team tested this new approach on five different chip designs that the tool had never seen before. The results were impressive. Compared to the standard, high-tech baseline method used in the industry (Hier-RTLMP), their new tool improved the chip's speed (measured as "worst negative slack") by 22% and its overall timing efficiency (measured as "total negative slack") by 51%. Crucially, it did this without making the chip use more power or become harder to build. They showed that by using this smart, learning-based guide, they could consistently outperform the hierarchical baseline and other evaluated prior methods, surpassing even the strong algorithmic approach of Re2MaP on average, proving that looking at the whole picture and learning from the final outcome is the key to building faster, more efficient chips.

Technical Summary: PPAPlace

Problem Statement

Chip placement is a critical step in physical design that determines the performance, power, and area (PPA) of a chip. While traditional analytical placers and recent artificial intelligence (AI) methods often optimize Half-Perimeter Wirelength (HPWL) as the primary objective, recent benchmarks (specifically ChiPBench) have revealed a near-zero correlation between HPWL and post-route timing metrics like Worst Negative Slack (WNS) and Total Negative Slack (TNS). Consequently, AI-based placers optimized for HPWL have been shown to degrade post-route PPA compared to hierarchical baselines.

Existing attempts to bridge this gap using cross-stage predictors face two significant limitations:

Label Fidelity: They rely on pre-route Static Timing Analysis (STA) or other pre-routing metrics as training labels, which do not faithfully reflect final post-route timing rankings.
Representation: They often represent the placement state using only macro positions, discarding crucial information regarding standard cell density and routing congestion that ultimately govern timing.

Methodology

The paper proposes PPAPlace, a timing-driven, differentiable surrogate model that predicts post-route PPA directly from the complete mixed-size placement state (macros and standard cells). The methodology consists of three core components:

1. Label Fidelity Analysis

Before designing the predictor, the authors conducted a controlled study across ten circuits and four design stages (Pre-CTS, Post-CTS, Post-Global-Routing, and Post-Detailed-Routing).

Finding: Pre-route timing labels (used in prior works like LaMPlace) showed poor correlation with final post-route rankings.
Conclusion: Post-Global-Routing (Post-GRT) labels offer the best balance between high fidelity to final timing (Spearman $\rho \approx 0.86$ ) and cost-effectiveness (0.20 hours per sample vs. 3.7 hours for full Post-Detailed-Routing).

2. Dual-Stream Differentiable Predictor

PPAPlace employs a dual-stream neural network architecture trained on Post-GRT labels to predict WNS, TNS, Power, and Area.

Spatial Stream: A Convolutional Neural Network (CNN) processes a $64 \times 64$ grid representation of the placement. This grid captures cell density, pin density, macro occupancy, RUDY-style congestion proxies, and net bounding box density.
Graph Stream: A Graph Attention Network (GAT) processes the netlist as a graph where macros are nodes. It encodes connectivity, macro dimensions, aspect ratios, and net spans.
Differentiability: The entire pipeline, from cell coordinates to feature extraction (using differentiable approximations like Gaussian splatting and log-sum-exp) to the final MLP prediction, is fully differentiable. This allows gradients of the predicted timing metrics to flow end-to-end back to the cell coordinates.

3. Gradient-Guided Deployment

The paper introduces two modes to exploit the predictor's gradients:

PPAPlace-CoOpt: The surrogate is injected as a co-objective into the analytical optimization loop of DREAMPlace. After a warm-up phase, the total loss function includes the predicted WNS and TNS gradients, guiding the global topology of both macros and standard cells.
PPAPlace-Refine: A post-placement refinement step that applies projected gradient descent to any converged legal placement. It adjusts macro positions to minimize the surrogate timing objective, followed by legalization and standard-cell re-optimization. This mode does not require access to the internal mechanics of the source placer.

Key Contributions

Label Fidelity Study: The paper establishes that Post-Global-Routing is the most cost-effective supervision stage for cross-stage PPA prediction, demonstrating that pre-route labels are often misleading.
Differentiable Dual-Stream Predictor: A novel architecture combining graph attention (netlist connectivity) and spatial convolution (density/congestion) that operates on the full mixed-size placement state. It achieves a Kendall's $\tau$ of 0.31 for WNS ranking, a significant improvement over macro-only, pre-route baselines (0.08).
Gradient-Guided Optimization: Two deployment strategies (CoOpt and Refine) that utilize end-to-end timing gradients to improve placement quality without retraining on test circuits.

Experimental Results

The method was evaluated on five held-out circuits from the ChiPBench suite (excluding the training set) and compared against the Hierarchical RTLMP baseline and other state-of-the-art methods (DREAMPlace, LaMPlace, Re2MaP, etc.).

Performance Gains: Using the combined CoOpt+Refine approach, PPAPlace improved average WNS by 22% and TNS by 51% over the hierarchical baseline.
Comparison: It outperformed all evaluated prior methods, including the algorithmic approach of Re2MaP.
Routability and Power: The improvements in timing were achieved while preserving routability (zero design-rule-check violations) and maintaining power consumption within a 1–2% variance.
Generalization: The model demonstrated strong zero-shot generalization to circuits with different macro counts and even different design families (e.g., Ariane CPUs not seen in training). It also showed significant, though slightly reduced, correlation when applied to placements generated by a different tool (RTLMP), indicating robustness across placement distributions.
Efficiency: The offline training cost is amortized, and the inference/refinement time adds minimal overhead (under 2.5x the standard DREAMPlace runtime).

Significance

The paper argues that optimizing placement requires moving beyond wirelength proxies and pre-route metrics. By validating that Post-GRT labels provide a reliable signal and constructing a differentiable surrogate that captures both connectivity and spatial congestion, PPAPlace demonstrates that learned, post-route timing objectives can effectively guide placement optimization.

The work establishes a principled basis for selecting supervision stages in cross-stage learning and proves that differentiable surrogates can be integrated into analytical placers or used as post-processing refinements to achieve state-of-the-art PPA results without the need for expensive full-flow evaluations during the optimization loop.