Evaluating the performance of QEC primitives on quantum processors at large width and depth

Quantum computers promise to solve problems that are currently impossible for classical machines, from designing new medicines to modeling complex climate systems. However, these machines are incredibly fragile. The quantum bits, or qubits, that hold information are easily disturbed by heat, vibration, and electromagnetic noise, causing them to lose their data almost instantly. To build a useful quantum computer, scientists must develop a way to protect this information, a process known as quantum error correction. This method involves constantly checking the qubits for mistakes without destroying the delicate quantum state, a task that requires a complex sequence of operations: measuring some qubits to see if an error occurred, resetting them, and then using that information to fix the others in real time. These steps are difficult to perform reliably, and until now, testing them has been slow, expensive, and required massive amounts of computing time.

A team of researchers has introduced a new, efficient way to test how well different quantum processors can handle these critical error-correction steps. Instead of running full, resource-heavy error-correction experiments that might take days or fail to produce clear results, the team developed a shortcut using a specific type of algorithm called the Quantum Approximate Optimization Algorithm. They adapted this algorithm so that its structure mimics the exact pattern of connections and measurements used in error correction, but with a twist: the algorithm produces a clear, measurable signal that gets weaker as errors accumulate. By running this adapted algorithm on various quantum processors, the researchers could quickly gauge how much the machines degrade when forced to perform the difficult task of measuring and resetting qubits mid-circuit. This approach allows scientists to compare different hardware generations and architectures without needing the immense resources required for a full-scale error-correction demonstration.

The researchers tested their method on ten different quantum processors from three major manufacturers: IBM, IQM, and Quantinuum. They began with a simple test involving a chain of qubits to see how the performance changed as they added more mid-circuit measurements. They found that on some machines, the signal remained strong even as the chain grew, while on others, the performance dropped off sharply. By translating the decay of the algorithm's signal into a single number representing an effective error rate, they could directly compare the cost of using mid-circuit measurements across different devices. For instance, on IBM's machines, the extra cost of performing these measurements was significantly higher than the cost of standard operations, whereas on Quantinuum's trapped-ion machines, the additional cost was much smaller and comparable to the errors found in standard two-qubit gates.

The study went further by testing the method against actual error-correction codes, including the surface code and color code, which are leading candidates for building fault-tolerant quantum computers. The team ran these tests on devices with up to 91 data qubits, a scale that would be extremely difficult to test with traditional methods. They discovered that the new benchmark could distinguish between different hardware generations and even identify which parts of a single chip were performing better than others. In a crucial validation step, they compared the results of their quick benchmark with the results of a full, slow error-correction memory experiment run on the same IBM processor. They found a strong correlation: the regions of the chip that performed well in the quick benchmark also showed the lowest error rates in the full memory experiment. This suggests that the new method can reliably predict how well a quantum processor will handle the complex demands of error correction.

The researchers also determined how many times they needed to run these tests to get a reliable answer. They found that for most devices, only a few dozen to a few hundred runs were enough to tell if the machine was still preserving the algorithmic signal or if it had collapsed into random noise. This is a dramatic reduction compared to the thousands or millions of runs often needed for traditional testing. The study indicates that as hardware improves and error rates drop, the tests will need to be run deeper and with more layers to see the differences, but the method remains efficient. By providing a practical, low-cost way to evaluate the readiness of quantum hardware for error correction, this work offers a vital tool for tracking progress in the field. It allows independent researchers and organizations to assess whether new quantum processors are truly advancing toward the goal of fault tolerance, without waiting for the full, expensive logical memory experiments to be completed.