⚡ electrical engineering

A Power-Efficient and Noise-Resilient Domino Logic Architecture with Adaptive Keeper Control for Wide Fan-In Applications

This paper proposes a power-efficient and noise-resilient domino logic architecture for wide fan-in applications that utilizes an adaptive keeper control scheme and a restructured PDN with a stacked footer transistor to significantly reduce power consumption, improve noise margins, and enhance robustness against process variations compared to conventional designs.

Original authors: Manoranjan Meher, Preetisudha Meher

Published 2026-06-24

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Manoranjan Meher, Preetisudha Meher

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are running a busy, high-speed factory assembly line. This factory is designed to make decisions incredibly fast, but it has a few annoying problems: it wastes a lot of electricity, it's easily confused by noise (like a sudden shout in the room), and it leaks energy even when it's trying to be quiet.

This paper introduces a new, smarter way to run this factory. The authors, Manoranjan and Preetisudha Meher, have designed a "Domino Logic" system (a type of electronic circuit used in fast computer chips) that fixes these problems.

Here is a simple breakdown of how their new design works, using everyday analogies:

The Problem: The "Over-zealous Security Guard" and the "Leaky Bucket"

In traditional fast circuits (called Domino Logic), there are two main issues:

The Security Guard Fight (Keeper Contention): Imagine a security guard (the "keeper") whose job is to keep a door locked so no one enters. But, sometimes, a worker (the "pull-down network") needs to open that door to let something out. In old designs, the guard keeps trying to hold the door shut while the worker is trying to open it. They end up wrestling, which wastes energy and slows everything down.
The Leaky Bucket (Subthreshold Leakage): Even when the factory is idle, the bucket holding the water (the electrical charge) has tiny holes. Water slowly drips out. If the bucket is too big (many inputs), the water leaks out so fast that the factory makes mistakes.

The Solution: A Smart Guard and a Reinforced Bucket

The authors propose two clever fixes to solve these problems:

1. The "Smart Security Guard" (Adaptive Keeper Control)

Instead of a guard who is always fighting the door, their new guard is smart and conditional.

How it works: The guard only steps in to hold the door shut if the worker isn't trying to open it. If the worker needs to open the door to do their job, the guard instantly steps aside and lets them go.
The Result: No more wrestling matches! This saves a huge amount of energy because the guard isn't wasting power fighting the worker. It also makes the system faster because the door opens immediately when needed.

2. The "Reinforced Bucket with a Double Bottom" (Modified Pull-Down Network)

To stop the water from leaking out, they changed the structure of the bucket.

How it works: Instead of a single pipe letting water out, they stacked two pipes on top of each other, with a special valve in between. This "stacking" creates a pressure effect that naturally blocks the tiny leaks.
The Twist: To make sure the water still flows fast when they want it to, they added a second, parallel pipe. This acts like a backup lane on a highway. When the main path is open, traffic (electricity) flows fast. But when the path is closed, the stacked pipes ensure the leaks stay tiny.
The Result: The bucket holds its water much longer (better noise resistance), but when it's time to empty it, it empties just as fast as before.

The Proof: The "128-Input Multiplexer" Test

To prove their idea works, the authors didn't just talk about theory; they built a massive test case. They created a 128-input Multiplexer.

The Analogy: Imagine a giant switchboard with 128 different phone lines. The system needs to pick one line to connect to the main phone. Doing this with 128 lines at once is usually very messy, slow, and power-hungry.
The Test: They built this switchboard using their new "Smart Guard" and "Reinforced Bucket" design and compared it to the old standard design.

The Results: What Did They Find?

When they ran the numbers on their 90-nanometer chip design, the results were impressive:

Power Savings: The new design used 34% less electricity. It's like getting the same work done but paying a much lower electric bill.
Noise Resistance: It became 54% better at ignoring outside noise. If someone shouted near the factory, the new system wouldn't get confused; the old one might have made a mistake.
Efficiency: They measured "Power-Delay Product" (a score that combines speed and energy). The new design scored 33% better, meaning it is much more efficient overall.
Reliability: Even when the temperature changed or the manufacturing wasn't perfect (process variations), the new design stayed stable. It didn't break down as easily as the old one.

In Summary

The authors created a smarter electronic circuit that stops its components from fighting each other and plugs the tiny leaks that waste energy. By doing this, they made a system that is faster, uses less power, and is much harder to fool by noise. They proved this works by building a massive 128-line switchboard that outperformed the traditional design in every major category.

This is a win for the future of portable devices and fast computers, as it allows them to run cooler and longer on a single battery charge.

Technical Summary: A Power-Efficient and Noise-Resilient Domino Logic Architecture with Adaptive Keeper Control for Wide Fan-In Applications

Problem Statement
Conventional domino logic (DLG) is widely utilized in high-speed VLSI circuits, particularly for wide fan-in applications, due to its compact layout and lower parasitic capacitance compared to static logic. However, as CMOS technology scales to nanometer nodes (e.g., 90 nm), DLG faces critical challenges. The reduction in supply voltage and threshold voltage ( $V_{th}$ ) leads to a significant increase in subthreshold leakage current, which can discharge the dynamic node, degrade noise margins, and cause logic errors. Furthermore, wide fan-in gates exacerbate these issues through increased charge sharing and contention between the pull-down network (PDN) and the keeper transistor. While increasing the keeper size improves noise immunity, it introduces severe contention currents during the evaluation phase, leading to higher power dissipation, increased delay, and sensitivity to process variations. Existing solutions, such as high-speed or conditional keeper architectures, often trade off robustness for speed, suffer from excessive area overhead, or fail to adequately suppress leakage in large fan-in configurations.

Methodology
The authors propose a modified domino logic gate (DLG) architecture designed to simultaneously address power dissipation, leakage, and noise resilience without compromising evaluation speed. The design, simulated using 90 nm CMOS technology in Cadence Virtuoso, incorporates two primary innovations:

Conditional Keeper Network: Unlike conventional static keepers that remain active throughout the evaluation phase, the proposed architecture employs a clock and data-dependent conditional keeper. This network is enabled only when the dynamic node is charged (indicating no active discharge path) and the clock is in the evaluation phase. When a valid discharge path is established in the PDN, the keeper is immediately disabled. This mechanism eliminates the contention current between the keeper and the PDN during valid logic transitions, thereby reducing dynamic power dissipation while preserving the dynamic node's stability against leakage and noise when the node should remain high.
Modified Pull-Down Network (PDN): To mitigate subthreshold leakage and charge sharing, the PDN is restructured using a stacked footer transistor configuration. Two NMOS transistors form parallel evaluation paths connected in series with a footer transistor. The stacked footer induces a body effect, raising the source potential of the upper transistors and increasing their effective threshold voltage ( $V_{TH,eff}$ ), which exponentially suppresses subthreshold leakage. To counteract the delay penalty typically associated with stacked transistors, a parallel transistor is introduced to provide an additional discharge path, ensuring that evaluation speed is maintained.

Key Contributions

Adaptive Keeper Control: The introduction of a keeper enable condition defined as $CLK \cdot \overline{PDN_{ON}}$ , which completely suppresses keeper-PDN contention during valid discharge events.
Leakage-Aware PDN Topology: A hybrid PDN structure combining a stacked footer for leakage suppression via body-effect modulation and parallel paths to minimize evaluation resistance.
Optimized Trade-off: The architecture achieves a favorable balance between power efficiency, noise immunity, and speed, specifically targeting wide fan-in OR logic applications.

Results
The proposed design was evaluated against several existing domino logic architectures (including SFDLG, DFDLG, HSDLG, VCDLG, VRKDLG, DOINDLG, FDSTDLG, and LPDLG) across 8, 16, 32, and 64-input configurations. Key simulation results for a 32-input OR gate include:

Power Consumption: A 34% reduction in average power consumption compared to the conventional SFDLG.
Noise Immunity: A 54% improvement in noise margin (measured via Unity Noise Gain Average, UNA).
Energy Efficiency: 33% reductions in both Power-Delay Product (PDP) and Energy-Delay Product (EDP).
Robustness: The design demonstrated improved tolerance to process, voltage, and temperature (PVT) variations, with lower standard deviations in delay and power compared to reference designs.
Multiplexer Implementation: A 128-bit wide fan-in multiplexer was implemented to validate the approach. The proposed design achieved a 32% reduction in power, a 21% improvement in noise margin, and a 32% reduction in PDP and EDP compared to a conventional domino-based multiplexer, with only a negligible increase in area (1.102x).

Significance
The paper claims that the proposed architecture offers a superior solution for contemporary energy-efficient wide fan-in dynamic logic applications, such as bit-line selection in memory and datapaths in superscalar microprocessors. By effectively decoupling the trade-off between noise robustness and contention-induced power dissipation, the design enables high-performance logic gates that are resilient to leakage and process variations without incurring significant area or speed penalties. The successful implementation of a 128-bit multiplexer further validates the scalability and practical applicability of the proposed adaptive keeper and modified PDN strategies in complex, large-scale VLSI systems.