⚡ electrical engineering

Time Domain Near Memory Computing Engine

This paper presents a time-domain near-memory computing architecture that converts digital weights and inputs into time-domain signals for efficient low-precision MAC operations, achieving 7.62 TOPS/W energy efficiency while balancing analog and digital design trade-offs to minimize peripheral overhead.

Original authors: Sarthak Antal, Steve Enosh

Published 2026-05-15

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Sarthak Antal, Steve Enosh

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are running a busy kitchen. In a traditional kitchen, the chef (the computer processor) has to constantly run back and forth to the pantry (the memory) to grab ingredients (data), cook them, and then run back to the pantry for the next batch. This running back and forth takes a huge amount of energy and time.

This paper proposes a new way to run the kitchen: Near-Memory Computing. Instead of the chef running to the pantry, we set up a small prep station right next to the pantry. The ingredients are already there, so the chef can start cooking immediately without the exhausting run.

However, the authors noticed that even with the prep station, the way we measure and mix ingredients can be inefficient. They propose two new ways to do the "mixing" (math) using Time instead of just standard electricity.

Here is the breakdown of their idea using simple analogies:

The Core Problem: The "Voltage" Bottleneck

Usually, computers do math by changing the height of a water level (voltage). If you want to be very precise, you need to measure tiny differences in water height. But measuring tiny differences requires huge, energy-hungry pumps and very large buckets (capacitors) to keep the water stable. As you try to get more precise, the energy cost goes up exponentially.

The Solution: The "Time" Switch

The authors say, "Why measure the height of the water? Let's measure how long the water flows."

They built a system where:

The Weights (Recipes): Stored in the memory, these are turned into a steady stream of water (current) by a special valve (a DAC).
The Inputs (Orders): These are turned into a timer. Instead of a specific water height, the system counts how many seconds the valve stays open.
The Multiplication: If you have a steady stream of water and you let it flow for a specific amount of time, the total amount of water collected is the result of the math.
- Analogy: Imagine filling a bucket. The "Recipe" determines how wide the tap is. The "Order" determines how long you leave the tap open. The total water in the bucket is the answer.

The Two "Mixing" Methods

Once the water is collected, they need to add up the results from many different recipes. They tested two ways to do this:

Method 1: The "Domino Chain" (Delay-Cell Architecture)

How it works: Imagine a line of dominoes. The first domino falls, which triggers the second, which triggers the third. In this system, the amount of water collected from each recipe controls how fast a specific domino falls.
The Process: You push the first domino, and it travels down the line. The total time it takes for the last domino to fall represents the sum of all the recipes.
The Pros: It's incredibly fast. You push once, and the answer comes out the other end almost immediately.
The Cons: If the dominoes aren't perfectly identical (which they rarely are in real life), the small errors add up. By the time the last domino falls, the timing might be a little off, making the final answer less accurate for big, complex calculations.

Method 2: The "Stopwatch Team" (Counter-Based Architecture)

How it works: Instead of a domino chain, imagine a team of people, each with their own stopwatch.
The Process: You ask Person A to time their domino fall and write down the number. Then you ask Person B to time theirs and write it down. You add all the numbers together on a piece of paper.
The Pros: Because everyone measures independently, a mistake by Person A doesn't mess up Person B's measurement. The final sum is very accurate and "linear" (predictable).
The Cons: It's slower. You have to stop, write down a number, move to the next person, and repeat. It takes more time and more "brain power" (control logic) to manage the team.

The Results

The team built a small prototype (a 4x4 kitchen station) to test these ideas.

Speed: They managed to run at 40 million times per second (40 MHz).
Efficiency: They used very little power (42 microwatts).
Efficiency Score: They achieved a score of 7.62 TOPS/W.
- Translation: For every tiny bit of energy they used, they got a massive amount of computing power. This is much better than standard digital chips for low-precision tasks (like the kind used in basic AI).

The Bottom Line

The paper claims that by switching from measuring "water height" (voltage) to measuring "water flow time," they created a computer chip that is much more energy-efficient for AI tasks.

If you need speed, the "Domino Chain" is great, but it gets a bit messy with complex math.
If you need accuracy, the "Stopwatch Team" is better, but it's slower.

The authors conclude that for now, the "Domino Chain" (Delay-Cell) approach is the winner for their prototype because it's faster and uses less control power, even though it has some limits on how precise it can be. They plan to try to fix the accuracy issues in future versions.

Technical Summary: Time Domain Near Memory Computing Engine

Problem Statement
The rapid growth of AI workloads has intensified the need for energy-efficient computing architectures, as data movement often consumes significantly more energy than the computation itself. While fully digital architectures offer robust scalability for high-resolution computation, they struggle with energy efficiency at sub-8-bit precision. Conversely, analog in-memory computing (IMC) demonstrates superior energy efficiency for low-precision workloads but suffers from the power, area, and design overheads associated with peripheral Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs). Furthermore, voltage-domain data converters face fundamental power-scaling limitations; improving resolution by 1 bit typically requires a 4× increase in power due to thermal noise constraints ($kT/C$) and reduced voltage headroom in scaled technologies.

Methodology
To address these challenges, this work proposes a time-domain near-memory computing architecture designed for low-precision Multiply-and-Accumulate (MAC) operations. The system maintains a digital-friendly interface while performing multiplication in the time domain. The core methodology involves:

Input Encoding: Digital input vectors are converted into time-domain signals using an N-pulse generator (implemented via RTL synthesis). The number of pulses generated is proportional to the input code (e.g., a 4-bit input of 1111 generates 16 pulses).
Weight Conversion: Digital weights stored in SRAM are converted to analog currents using a 4-bit current-steering DAC (CSDAC).
Multiplication: The multiplication operation is realized by integrating the DAC output current ( $I_{DAC}$ ) over the pulse duration ( $T_{pulse}$ ) generated by the N-pulse generator onto a capacitor. The resulting voltage is $V_{MAC} = (I_{DAC} \cdot T_{pulse}) / C$ .
Accumulation Schemes: Two distinct architectures for accumulating these time-domain products are investigated and compared:
- Architecture I (Delay-Cell-Based): Uses a cascaded chain of current-starved inverters. The voltage from each MAC operation controls the delay of a subsequent stage. The total delay of the chain represents the accumulated sum.
- Architecture II (Counter-Based): Measures the delay of each multiplication cell independently using a counter. The individual delay counts are then summed digitally. This approach avoids cascading nonlinear delay stages.

Key Contributions

Hybrid Time-Domain Approach: The paper presents a novel architecture that leverages the energy efficiency of analog computing while mitigating the overhead of high-resolution voltage-domain converters by operating in the time domain.
Dual Accumulation Analysis: A detailed comparative analysis of two accumulation strategies: a high-throughput, cascaded delay-line approach versus a high-linearity, counter-based approach.
RTL-Analog Co-Design: The N-pulse generator and counters are implemented using RTL synthesis to ensure technology portability, while the current-steering DAC remains in the analog domain.
Prototype Implementation: A 4×4 MAC prototype was implemented in a 65 nm process with a 1 V supply.

Results
The proposed 4×4 MAC prototype operates at 40 MHz with a power consumption of 42 µW, achieving an energy efficiency of 7.62 TOPS/W.

Linearity vs. Throughput Trade-off:
- The counter-based architecture demonstrates superior linearity, closely following the ideal response because it prevents the propagation of delay errors from one stage to the next. However, it suffers from timing quantization noise and requires sequential measurement, leading to lower throughput and higher digital control overhead.
- The delay-cell-based architecture offers higher throughput and lower control overhead by performing accumulation in a single propagation event. However, simulation results indicate that as the matrix dimension increases, the nonlinear characteristics of the cascaded delay cells accumulate, causing significant deviation from the ideal linear response.
Design Constraints: The system is constrained by the linear operating range of the PMOS current-starving devices (approx. 300 mV). Consequently, the current implementation is limited to 4-bit precision.

Significance and Claims
The paper claims that time-domain near-memory computing offers a promising alternative for low-precision AI workloads by circumventing the power-scaling limitations of voltage-domain data converters. The authors position their work as a step toward energy-efficient edge AI, noting that while the current 4-bit resolution limits immediate applicability to high-precision tasks, the architecture provides a foundation for future scaling.

The authors modestly acknowledge that the current design is limited by linearity issues in the delay-cell approach and resolution limits in the counter-based approach. They do not claim immediate superiority over all state-of-the-art works but highlight that the delay-cell-based architecture (used for the reported performance metrics) provides a favorable balance of operating frequency and control overhead. Future work is identified as focusing on improving linearity through bias optimization, RC-based delay cells, and calibration techniques to potentially extend the architecture to 8-bit operation.