🤖 machine learning

ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

This paper introduces ParasGB, the first open-source benchmark suite featuring large-scale, high-fidelity RC networks from tape-out-proven designs to enable reproducible evaluation and address challenges in graph neural network-based pre-layout parasitic estimation for analog and mixed-signal circuits.

Original authors: Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu

Published 2026-07-28

📖 8 min read🧠 Deep dive

CC BY 4.0

Original authors: Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are building a massive, intricate city out of LEGO bricks. In the early stages of planning, you sketch out where the roads, houses, and parks should go. You might think, "This road looks short, so cars will zip through it quickly." But in the real world, once you actually build the city, you realize the roads are narrower than you thought, there are unexpected traffic lights, and the ground beneath them is squishy, slowing everything down. In the world of computer chips, this "squishy ground" and "narrow roads" are called parasitics. They are tiny, unwanted electrical effects—like invisible resistance and capacitance—that sneak in when a chip is physically built. These effects can turn a fast, efficient design into a sluggish, overheating mess.

For decades, chip designers have had to wait until the very end of the process, after they've spent months and millions of dollars building the physical layout, to measure these parasitics. If the chip is too slow, they have to tear it down and start over, a bit like realizing your LEGO city is too heavy for the table only after you've glued every single brick. This is a slow, expensive game of "guess and check." Recently, scientists have started using a type of artificial intelligence called Graph Neural Networks (GNNs) to predict these problems early. Think of a GNN as a super-smart detective that looks at the blueprint (the schematic) and tries to guess what the finished city will look like, including all the hidden traffic jams, before a single brick is laid. However, until now, there was no fair way to test if these AI detectives were actually good at their job because everyone was using different, secret blueprints to train them.

This paper introduces ParasGB, a new, open-source "training ground" for these AI detectives. The researchers created a massive, standardized library of real-world chip designs that have already been successfully built and tested (a process called "tape-out"). They extracted the exact electrical data from these real chips and turned them into a giant puzzle for AI to solve. The paper finds that while standard AI models struggle with this task—often getting confused by the extreme differences in how big or small these electrical effects can be—specialized models designed specifically for chip circuits perform much better. The authors show that by using this new benchmark, we can finally compare different AI methods fairly and identify which ones are truly ready to help designers build faster, better chips without wasting time on costly mistakes.

The Story of ParasGB

The Problem: The "Ghost" in the Machine

Imagine you are designing a race car. You draw the perfect engine and aerodynamic body on paper. But you don't know that the metal you'll use is slightly heavier than you thought, or that the wind will hit the car differently once it's actually moving. In chip design, these "ghosts" are parasitic resistance and capacitance. Resistance is like friction slowing down electricity, and capacitance is like a sponge soaking up electrical charge. In modern chips, which are smaller than a grain of sand, these effects are huge. They can account for up to 80% of the delay in a signal's journey.

Traditionally, designers only find out about these ghosts after they finish the physical layout. If the chip is too slow, they have to go back and redesign, which is like rebuilding the race car's engine after the race has already started. This cycle is slow and incredibly expensive. The goal of this research is to predict these ghosts before the chip is built, using AI to look at the blueprint and say, "Hey, this wire is going to be too narrow, and that part will get too hot."

The Missing Piece: A Fair Test

For a while, researchers have been trying to build AI models (specifically Graph Neural Networks) to predict these parasitics. But there was a big problem: there was no common test to see who was the best. It was like having five different driving schools, each testing their students on a different, secret track. Some used tiny tracks, some used huge ones; some had dirt, some had ice. Without a standard track, you couldn't tell if a student was a good driver or just lucky.

The paper argues that previous attempts were stuck because they relied on small, outdated, or private data. You can't build a world-class AI if you only train it on toy cars. The researchers needed a massive, high-quality dataset from real, working chips to train and test these models fairly.

The Solution: ParasGB

Enter ParasGB. The authors created the first open-source benchmark suite for this specific task. They gathered data from real chips that had already been manufactured and proven to work. These chips include both Analog circuits (which handle continuous signals like sound or radio waves) and SRAM (the memory chips that store data in your phone or computer).

They took these real designs, which were created using professional industry tools, and converted them into "graphs." In this graph, the electronic components (like transistors) are the nodes (dots), and the wires connecting them are the edges (lines). The "labels" or answers they want the AI to predict are the exact values of resistance and capacitance for every part of the graph.

The dataset is huge and varied:

Analog Circuits: These range from tiny blocks with 231 nodes to larger modules with nearly 7,000 nodes. The values here are incredibly tiny, often in the range of $10^{-14}$ to $10^{-13}$ Farads (a unit of capacitance).
SRAM Circuits: These are the giants. The smallest SRAM design in the set has about 17,600 nodes, while the largest has a staggering 11.7 million nodes and 55.2 million edges.

This variety is crucial. It forces the AI to learn how to handle both tiny, delicate circuits and massive, complex ones.

The Challenges: The "Long Tail"

The paper highlights a few tricky hurdles that make this task hard for AI. One major issue is label imbalance. In the real world, most wires have very small resistance or capacitance, but a few critical wires have huge values. It's like a classroom where 99% of students have 100 points, but one student has 1,000,000 points. If an AI just guesses "100" for everyone, it might get a high average score, but it will completely miss the one student who actually needs help. The paper shows that these "extreme" values are often the most important for the chip's performance, yet they are rare.

Another challenge is structural heterogeneity. Every chip looks different. One might be a dense forest of connections, while another is a sparse grid. An AI that learns to predict one type of chip might fail miserably on another.

The Experiments: Who Wins the Race?

The researchers tested many different AI models on this new benchmark. They compared "general" graph models (which are good at many things but not specialized for chips) against "circuit-specific" models (which are built with knowledge of how electronics work).

The results were clear:

General Models: Standard AI models like GCN and GAT struggled, especially with the most difficult circuits. On some hard analog circuits, they performed so poorly that their predictions were worse than random guessing (indicated by negative scores).
Specialized Models: Models designed specifically for circuits, such as CircuitGCL and CircuitGPS, performed significantly better. For example, on the task of predicting coupling capacitance (how much wires interfere with each other) in SRAM chips, CircuitGCL consistently achieved the highest accuracy and F1-scores across all test cases.
The "Hard" Cases: The paper notes that the biggest gains were seen on the most difficult circuits. Where general models failed, the specialized models managed to turn negative predictions into positive ones, proving that understanding the specific physics of the circuit helps the AI make better guesses.

What This Means

ParasGB isn't just a dataset; it's a new standard. It provides a "gold standard" for researchers to test their ideas. By using real, tape-out-proven data, it bridges the gap between academic theory and real-world engineering. The paper suggests that while we are making progress, the field still faces significant challenges with data imbalance and the sheer complexity of different chip designs.

However, the path forward is clearer now. With a unified benchmark, researchers can stop reinventing the wheel and start focusing on building better, more robust AI models. These models could eventually help chip designers predict problems early, reducing the number of costly redesigns and speeding up the creation of the next generation of faster, more efficient electronics. The paper concludes that while this is a big step, it's just the beginning, and future work will need to expand to cover even more types of chips and process technologies.

Technical Summary: ParasGB

Problem Statement
As chip manufacturing advances to deep submicron nodes (7nm and below) and 3D IC technologies emerge, parasitic interconnect effects (resistance $R$ and capacitance $C$ ) have become a primary bottleneck for Analog and Mixed-Signal (AMS) and memory circuit design. Unlike digital design, where layout is automated, AMS and memory layouts are often manual and time-consuming. The impact of parasitics is typically only captured accurately during post-layout extraction, leading to costly design iterations if performance metrics are missed. Early-stage parasitic estimation is crucial for guiding design decisions (e.g., driver sizing, buffer insertion, floorplanning) before layout finalization. However, progress in Graph Neural Network (GNN)-based parasitic modeling has been stalled by a lack of public, high-fidelity benchmarks. Existing datasets are either limited to digital circuits, schematic-level analog tasks, or lack post-layout RC supervision, creating isolated data islands that hinder reproducible research and fair algorithm comparison.

Methodology
The paper introduces ParasGB, the first open-source benchmark suite for pre-layout parasitic parameter prediction on circuit graphs. The methodology encompasses dataset construction, graph representation, and a standardized evaluation framework:

Dataset Construction: ParasGB utilizes data from real, tape-out-proven designs generated via commercial EDA toolchains.
- Analog Subset: Derived from a 180nm BCD process using Cadence Virtuoso/Spectre and Siemens Calibre xRC. It includes 20 designs (LVDS, BGR, OP, LDO) ranging from micro-scale blocks to complex modules.
- SRAM Subset: Derived from a TSMC 28nm process using HSPICE/FineSim and Synopsys StarRC. It includes 6 subsets (e.g., digtime, sandwich, ultra8t) ranging from ~18k to ~11.7M nodes.
Graph Representation: The framework converts post-layout netlists into heterogeneous graphs ( $G=(V, E)$ $G = (V, E)$ ).
- Nodes: Three types are defined: Device nodes (MOSFETs, resistors), Net nodes (interconnects), and Pin nodes (terminals).
- Edges: Topological edges capture schematic connectivity ($dev2pin$, $pin2net$). Supervision edges include effective resistance ( $R_{eff}$ ) and coupling capacitance ( $C_c$ ).
- Feature Engineering: Schematic-level attributes are encoded as node features (device geometry, net connectivity, pin roles) to approximate unobserved layout-dependent parasitics.
- Label Generation: Distributed RC networks are simplified into lumped models. Nodes are labeled with ground capacitance ( $C_g$ ), while edges are labeled with $R_{eff}$ (computed via matrix-based methods) and $C_c$ (aggregated for SRAM).
Task Formulation: The benchmark defines multi-level tasks:
- Granularity: Node-level ( $C_g$ ) and Edge-level ( $R_{eff}$ , $C_c$ ).
- Objectives: Both regression (fine-grained estimation) and classification (magnitude binning) are supported.
Preprocessing: To address extreme label imbalance and long-tailed distributions, the framework applies logarithmic scaling, percentile-based normalization, and clipping to the $[0, 1]$ interval.

Key Contributions

High-Quality Dataset: Publication of a dataset derived from commercial EDA flows with gold-standard parasitic labels, covering both analog and SRAM designs across multiple scales.
Comprehensive Benchmark Suite: A unified evaluation protocol covering node/edge-level regression and classification for $C_g$ , $R_{eff}$ , and $C_c$ .
Research Framework: An easy-to-use toolkit (based on PyTorch Geometric) that mimics the Open Graph Benchmark (OGB) style, providing standardized data loading, automatic scoring, and reproducible training pipelines.
Challenge Identification: The benchmark explicitly exposes critical challenges in the domain, including extreme label imbalance, long-tailed parasitic distributions, and strong structural heterogeneity across different circuit topologies.

Experimental Results
The authors benchmarked diverse GNN architectures, including general-purpose models (GCN, GAT, GraphSAGE, PNA, SGFormer, PolyNormer) and circuit-specific models (CircuitGPS, CircuitGCL).

SRAM Tasks: For edge-level coupling capacitance classification, CircuitGCL consistently outperformed other models across all subsets, achieving the highest Accuracy and F1-scores. This suggests that modeling dense local coupling structures with circuit-specific inductive bias is critical. For node-level ground capacitance classification, performance varied by subset, with PolyNormer, CircuitGCL, and SGFormer showing strengths in different designs, highlighting the heterogeneity of SRAM patterns.
Analog Tasks: In regression tasks, $C_g$ prediction was generally more stable than $R_{eff}$ prediction. While general models performed well on $C_g$ , $R_{eff}$ prediction remained challenging, particularly on specific circuits (e.g., ID 14) where general models yielded negative $R^2$ . Circuit-specific models (CircuitGPS, CircuitGCL) demonstrated significant improvements on these difficult cases, turning negative $R^2$ values into positive ones.
General Observations: The results confirm that circuit-specific models designed for parasitic tasks generally outperform general-purpose GNNs, especially on hard-to-predict cases. However, the persistent gap between Accuracy and F1-scores in classification tasks underscores the difficulty posed by label imbalance.

Significance and Claims
The paper claims that ParasGB fills a critical gap in EDA research by providing a physically grounded, standardized platform for reproducible research on circuit graph learning. By establishing a unified benchmark with high-fidelity data, it enables:

Fair comparison of algorithms across different circuit domains and scales.
The study of model robustness and generalization in parasitic-aware design.
The development of more effective graph foundation models tailored to circuit-specific tasks.

The authors position ParasGB not as a replacement for full post-layout extraction, but as a tool to accelerate early-stage design exploration and reduce iteration cycles. They acknowledge limitations, noting the current scope is restricted to specific process nodes and circuit families, and that detailed placement/routing geometry is not explicitly modeled, but view the suite as a foundational step toward bridging the gap between academic benchmarks and industrial realities.