Comparison of spin-qubit architectures for quantum error-correcting codes

Technical Summary: Comparison of Spin-Qubit Architectures for Quantum Error-Correcting Codes

Problem Statement
The realization of large-scale, fault-tolerant (FT) quantum computing requires physical qubit error rates below $10^{-10}$, a threshold unlikely to be met by physical qubits alone. Consequently, quantum error correction (QEC) is essential to encode logical qubits non-locally across multiple physical qubits. While superconducting and trapped-ion platforms have demonstrated QEC, spin qubits in semiconductor quantum dots (QDs) offer superior scalability and compatibility with existing fabrication technologies but lag in experimental QEC demonstrations.

This study addresses the specific challenges of implementing distance-3 QEC codes on silicon spin-qubit platforms. It investigates how different qubit encoding schemes and code architectures perform under state-of-the-art experimental parameters. Specifically, the paper compares:

1. Encoding Schemes: A pure Loss-DiVincenzo (LD) scheme (single-electron Zeeman qubits) versus a hybrid scheme (LD data qubits combined with singlet-triplet (ST) ancilla qubits).
2. QEC Codes: The surface code (rotated) and the Bacon-Shor (BS) code.

The primary goal is to identify dominant error mechanisms, determine optimal hardware parameters, and evaluate whether logical qubits can currently outperform physical qubits (reach the "break-even" point) in this architecture.

Methodology
The authors employ a circuit-based stabilizer simulation framework to model fault-tolerant procedures.

• Physical Platform: The simulations are based on silicon QD parameters, specifically Si/SiGe quantum wells. Two encoding types are modeled:
  • LD Qubits: Single-electron spins controlled via ESR/EDSR, with readout via energy-selective tunneling.
  • ST Qubits: Two-electron spins in double QDs, controlled via exchange coupling and magnetic field gradients, with readout via Pauli spin blockade (PSB).
• Hybrid Architecture: The proposed layout uses LD qubits for data storage (leveraging longer coherence times) and ST qubits for ancilla (leveraging faster readout speeds).
• Noise Model: The simulation incorporates stochastic Pauli error channels including:
  • State preparation and measurement errors.
  • Single-qubit gate errors (modeled as Y errors after $\pm \pi/2$ rotations).
  • Two-qubit gate errors (modeled as ZZ errors after CZ gates).
  • Memory (idle) errors modeled as Gaussian dephasing ($T_2^*$) dependent on operation duration.
• Simulation Techniques:
  • Stabilizer Formalism: Used for efficient classical simulation of Clifford circuits.
  • Importance Sampling: An error-subset sampler is utilized to efficiently estimate logical error rates at low physical error probabilities by focusing on the most likely error configurations.
  • Procedures Simulated:
    1. FT QEC Step: A single round of stabilizer measurements (potentially adaptive with a second round) to detect and correct errors.
    2. FT Logical State Preparation: Preparation of logical $|0\rangle_L$ and $|+\rangle_L$ states. For the surface code, this is projective; for the BS code, it is unitary (coherent) via GHZ state preparation, provided specific connectivity exists.

Key Contributions and Results

1. Superiority of Hybrid Encoding:
   The hybrid scheme (LD data + ST ancilla) consistently outperforms the all-LD scheme by more than an order of magnitude. The primary driver is the significantly shorter readout duration of ST qubits ($2.4 \, \mu\text{s}$) compared to LD qubits ($24 \, \mu\text{s}$). In the all-LD scheme, the long readout time causes data qubits to fully dephase before error correction is completed, rendering the logical qubit ineffective. The hybrid scheme reduces this idle time, preserving coherence.

2. Dominance of Gate Errors over Memory Errors:
   A critical finding is that for distance-3 codes in this hybrid architecture, the logical error rate is fundamentally limited by gate infidelities (single- and two-qubit gates), not by memory (dephasing) errors. Even with state-of-the-art coherence times, the logical error rate saturates at a floor determined by gate errors. This suggests that for near-term proof-of-concept experiments, improving gate fidelity is more impactful than extending coherence times.

3. Optimization of Readout Integration Time:
   The study identifies a trade-off in ST qubit readout: longer integration times improve readout fidelity but increase idle time for data qubits, leading to dephasing. The authors find that the integration time minimizing the logical error rate ($\approx 0.88 \, \mu\text{s}$) is shorter than the time minimizing the readout infidelity ($\approx 1.4 \, \mu\text{s}$). At the current state-of-the-art integration time ($2.0 \, \mu\text{s}$), the hybrid logical qubit slightly outperforms a bare physical LD qubit (without spin-echo protection).

4. Comparison of Surface vs. Bacon-Shor Codes:

   • QEC Step: The surface-17 code yields a slightly lower logical failure rate than the BS-17 code during the error correction step. This difference is attributed to the classical decoding process, as the quantum circuits for measuring stabilizers are identical for both codes in this layout.
   • State Preparation: The BS-17 code demonstrates a massive advantage (nearly 2 orders of magnitude) in preparing logical $|0\rangle_L$ and $|+\rangle_L$ states. This is because the distance-3 BS code allows for fully coherent (unitary) preparation via GHZ states, whereas the surface code requires projective stabilizer measurements. This advantage requires a connectivity of 6 (hexagonal layout) to allow direct entangling gates between neighboring data qubits in the same row.

5. Parameter Sensitivity:
   The logical error rate is most sensitive to single-qubit gate infidelities ($p_{1q}$) and two-qubit gate infidelities ($p_{CZ}$). A simultaneous reduction of these errors by a factor of 10 could lower the logical error rate below $10^{-3}$.

Significance and Claims
The paper claims to provide a concrete roadmap for improving spin-qubit hardware for QEC. It highlights that:

• Hardware Targets: The primary bottleneck for logical error rates in distance-3 codes is gate infidelity, specifically single-qubit and two-qubit gates.
• Architecture Design: Hybrid encoding (LD data, ST ancilla) is essential to mitigate dephasing during measurement cycles.
• Code Selection: While the surface code is slightly better for error correction, the Bacon-Shor code offers a distinct advantage for logical state preparation, provided the hardware supports the necessary connectivity (direct row-wise entanglement) for coherent GHZ state generation.
• Feasibility: With current state-of-the-art parameters, a hybrid logical qubit can achieve a lower error rate than a physical qubit, marking a potential break-even point for distance-3 codes.

The authors remain modest regarding scalability, noting that for higher-distance codes, memory errors will likely become dominant, and spatial/temporal noise correlations (not included in this study) will need to be addressed. They also note that the Bacon-Shor code's advantage in state preparation relies on specific connectivity that may be challenging to implement in standard 2D arrays without electron shuttling or triangular lattice designs.