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PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL

This paper presents the design, specifications, and simulation results of PSEC6, an 8-channel 40 GSa/s waveform sampling ASIC fabricated in TSMC 65nm technology that features a novel 10.24 GHz PLL and achieves picosecond-level timing resolution for advanced particle physics applications.

Original authors: Ahan Datta, Andrew Arzac, Davide Braga, Gordon Chen, Troy England, Farah Fahim, Henry J. Frisch, Nathan Gehl, Mary Heintz, Sumin Kim, Ava Lalich, Jinseo Park, Nathaniel J. Pastika, Hector D. Rico-Anil
Published 2026-08-21
📖 6 min read🧠 Deep dive

Original authors: Ahan Datta, Andrew Arzac, Davide Braga, Gordon Chen, Troy England, Farah Fahim, Henry J. Frisch, Nathan Gehl, Mary Heintz, Sumin Kim, Ava Lalich, Jinseo Park, Nathaniel J. Pastika, Hector D. Rico-Aniles, Paul M. Rubinov, Xiaoran Wang, Y. M. Richmond Yeung

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the world of high-energy physics, where scientists smash particles together to understand the fundamental building blocks of the universe, time is the most critical ruler. When particles collide, they create fleeting flashes of light and energy that vanish in a fraction of a second. To reconstruct what happened, researchers must measure exactly when these flashes occur with incredible precision. If the timing is off by even a tiny fraction, the picture of the event becomes blurry, and scientists might miss crucial details about how particles interact or where they originated. This need for extreme temporal accuracy drives the development of specialized electronics capable of capturing signals at speeds that far exceed the blink of an eye. The goal is to create a system that can record these rapid events clearly, without losing data or introducing errors, allowing physicists to see the universe with sharper focus than ever before.

A team of researchers has developed a new electronic chip designed to meet these demanding requirements, pushing the boundaries of what is possible in capturing fast-moving signals. This chip, known as PSEC6, acts as a high-speed camera for electrical signals, capable of taking snapshots of voltage changes at a rate of 40 billion times per second. To put this speed into perspective, if the chip were to take one snapshot every second, it would take over a thousand years to reach the same number of samples it captures in a single second. The device was built using a standard manufacturing process for computer chips, yet it achieves a level of performance that was previously difficult to reach in this specific technology. The researchers successfully designed and simulated the chip's behavior, confirming that it can handle the extreme speeds required for modern particle physics experiments while maintaining the stability needed for accurate measurements.

The core challenge in building such a device lies in balancing speed with the ability to hold onto data long enough to be read later. The chip contains eight separate channels, each acting as an independent recording station. Inside each channel, the chip uses a method called a switched capacitor array, which works like a series of tiny buckets that catch and hold a drop of water representing an electrical signal. The innovation here is the use of two different types of these recording banks. One set of banks captures data extremely quickly over a very short period, while another set records more slowly over a much longer duration. This dual approach allows the chip to catch the sharp, fast details of a particle collision while also keeping a long-term record of the background noise, which helps scientists calibrate their instruments and distinguish real signals from static. The fast banks can capture a window of time lasting just 1.6 billionths of a second, while the slow bank can record a continuous stream for over 200 billionths of a second.

To drive this rapid sampling, the chip relies on a highly precise internal clock, a component known as a phase-locked loop. This clock generates a signal that oscillates at a frequency of 10.24 billion cycles per second, which is the heartbeat that tells the sampling switches when to open and close. Creating such a fast and stable clock inside a standard computer chip is difficult because high speeds often lead to jitter, or tiny, random variations in timing that can blur the data. The team designed a custom clock system that minimizes these variations, predicting a timing stability so fine that the error is measured in femtoseconds, a unit of time so small it is hard to imagine. The simulations suggest that this clock system consumes very little power, making it efficient enough to be used in large arrays of detectors without draining excessive energy.

The path the electrical signal takes through the chip is also carefully engineered to preserve the shape of the data. As the signal enters the chip, it passes through buffers that amplify it without distorting its shape, ensuring that the fast rising edges of the signal are captured accurately. The design team chose specific types of transistors, the tiny switches that control the flow of electricity, to handle the high voltages required for fast switching while maintaining a wide bandwidth. This bandwidth, which determines how much of the signal's frequency spectrum can be captured, is predicted to reach 4 gigahertz. This means the chip can faithfully reproduce signals that change very rapidly, a necessity for resolving the fine details of particle interactions. The output of the chip remains in an analog form, meaning it is a continuous electrical wave, which is then sent to an external device to be converted into digital numbers for computer analysis.

Power consumption is a major concern in these experiments, as large detectors can contain thousands of these chips. The simulations indicate that each of the eight channels on the PSEC6 chip consumes about 20 milliwatts of power while sampling, a relatively low amount for such high performance. The internal clock system adds another 15.7 milliwatts. The entire chip occupies a very small area, roughly 2.7 square millimeters, yet it integrates complex digital controls, analog signal paths, and the high-speed clock all on a single piece of silicon. The design includes features to protect the delicate internal circuits from electrical surges and to manage the heat generated during operation.

The researchers have completed the design and simulation phases of the project and have sent the specifications to a manufacturer to have the physical chips produced. The simulations predict that the chip will achieve the desired timing resolution and bandwidth, but the final proof will come only when the physical device is tested in a laboratory. The team is currently preparing the equipment and methods needed to test the chip once it arrives from the factory. If the physical results match the simulations, this new chip will provide a powerful tool for future experiments, enabling scientists to measure time with a precision that was previously out of reach. The work represents a significant step forward in the engineering of electronics for science, demonstrating that it is possible to build highly specialized, ultra-fast instruments using standard manufacturing techniques.

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