🔬 materials science

Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles

This paper presents an extended quantum transmitting boundary method (QTBM) that efficiently computes ab initio gate leakage currents in ultra-scaled WS $_2$ -hBN field-effect transistors by overcoming challenges in open boundary conditions and unstructured sparse linear systems, thereby outperforming state-of-the-art techniques for devices with gate lengths exceeding 25 nm.

Original authors: Mauro Dossena, Nicolas Vetsch, Alexander Maeder, Anders Winka, Vincent Maillou, Denghui Lu, Alexandros Nikolaos Ziogas, Jiang Cao, Mathieu Luisier

Published 2026-11-02

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CC BY 4.0

Original authors: Mauro Dossena, Nicolas Vetsch, Alexander Maeder, Anders Winka, Vincent Maillou, Denghui Lu, Alexandros Nikolaos Ziogas, Jiang Cao, Mathieu Luisier

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the relentless drive to make electronic devices smaller and faster, engineers face a fundamental physical hurdle: the gate. In a modern transistor, the gate acts as a switch, controlling the flow of electricity through a channel. To make the switch more sensitive and responsive, the insulating layer beneath this gate must be made incredibly thin. However, when this layer becomes too thin, electrons begin to tunnel. Instead of obeying the rules of the switch and staying within their designated path, they quantum mechanically tunnel through the insulator and leak into the gate. This leakage wastes energy and generates heat, potentially rendering future generations of ultra-small computers inefficient or even useless. To design better devices, scientists must be able to predict exactly how much current will leak, but calculating this for the tiny, complex materials used in next-generation chips has long been a computational nightmare.

A team of researchers at ETH Zurich has now developed a new way to solve this problem, allowing them to simulate gate leakage in transistors that are far larger and more realistic than previously possible. Their work focuses on a specific type of future transistor built from a sandwich of materials: a channel made of tungsten disulfide, an insulating layer of hexagonal boron nitride, and a metal gate made of platinum. In these devices, the gate sits directly on top of the channel, creating a vast area where electrons can escape. The challenge for computer scientists is that the mathematical equations required to track these escaping electrons become so complex and numerous that standard supercomputers run out of time and memory before they can finish the calculation, especially when the gate is longer than a few nanometers.

The researchers tackled this bottleneck by changing how they approached the mathematics of the problem, breaking it down into two manageable parts. First, they realized that treating the entire gate as one massive, solid block was unnecessary and inefficient. Instead, they divided the gate into smaller, repeating units. By calculating the behavior of just one small unit and then mathematically stitching these results together, they could model the entire gate without having to solve the impossible equations for the whole thing at once. This approach is similar to how one might estimate the total weight of a long chain by weighing a single link and multiplying, rather than lifting the entire chain.

Second, they addressed the issue of the messy, unstructured data that arises when electrons interact with the gate. Standard methods for solving these equations create a "fill-in" effect, where the computer's memory gets clogged with unnecessary data, slowing everything down. The team introduced a technique that simplifies the description of the gate's influence, stripping away the redundant information while keeping the essential physics intact. This allowed them to use a more efficient algorithm to solve the remaining equations, turning a problem that would have required hours or days of computing time into one that could be solved in minutes.

The results of this new method are striking. The researchers tested their approach on a transistor with a gate length of 6.4 nanometers, comparing their simplified calculations against a full, rigorous simulation. The results matched almost perfectly, proving that their shortcuts did not sacrifice accuracy. Encouraged by this validation, they pushed the simulation to a gate length of 25.6 nanometers, a size that is representative of real-world devices but was previously too large to simulate with this level of detail. They successfully calculated how electrons tunnel from the source and drain into the gate, identifying specific energy levels where leakage is most likely to occur.

This work demonstrates that it is now possible to model gate leakage in ultra-scaled transistors with high precision, even when the gate extends over a significant portion of the channel. By combining these two mathematical innovations, the team has removed the computational barrier that previously limited such studies to tiny, artificial structures. This capability opens the door for engineers to test different combinations of materials and gate designs on a computer before building them in a lab, ensuring that future transistors can be made smaller and more efficient without succumbing to the problem of leaking current.

Technical Summary: Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles

Problem Statement
As transistor dimensions and equivalent oxide thickness (EOT) continue to miniaturize, gate leakage currents are emerging as a critical limiting factor for future technology nodes. This issue is particularly acute for logic switches utilizing two-dimensional transition metal dichalcogenides (TMDCs), such as WS2, which lack intrinsic oxides. While ab initio quantum transport (QT) solvers have been employed to study semiconductor-dielectric interfaces, they have not previously been effectively applied to gate leakage. Conventional QT tools typically model carrier injection only at the source and drain. Introducing a third injection path at the gate—a large spatial region extending across the entire channel—creates two significant computational bottlenecks:

Open Boundary Conditions (OBCs): Calculating the self-energy and injection matrices for the gate contact involves solving non-linear eigenvalue problems (NEVPs). The computational cost of these NEVPs scales cubically ( $O(N^3)$ ) with the number of orbitals, making calculations for long gate electrodes prohibitively expensive.
Linear System Solution: The presence of the gate contact alters the sparsity pattern of the system matrix ( $ES - H - \Sigma_B$ ), rendering it unstructured. This unstructured pattern causes excessive "fill-in" during direct LU factorization and prevents the efficient application of standard block Gaussian elimination techniques like the recursive Green's function (RGF) algorithm.

Methodology
To address these challenges, the authors extend the Quantum Transmitting Boundary Method (QTBM) using two primary approximations:

Bloch Expansion of Open Boundary Conditions:
To mitigate the cubic scaling of the NEVP, the full gate contact (Full Cell, FC) is decomposed into smaller, repeatable unit cells (UC). By assuming periodicity along the transverse directions, the authors apply a Bloch expansion. They compute the boundary self-energy ( $\sigma^B_G$ ) and injection matrix ( $inj_G$ ) for a single unit cell across a grid of auxiliary wave vectors ( $k_a, k_b$ ). These are then reconstructed to form the full contact matrices ( $\Sigma^B_G$ and $Inj_G$ ) using Kronecker products. While exact for infinite periodic cells, this serves as a validated approximation for finite gate lengths.
Low-Rank Decomposition of the System Matrix:
To handle the unstructured sparsity, the gate self-energy matrix $\Sigma^B_G$ is approximated using a low-rank decomposition ( $\Sigma^B_G \approx R_G \Lambda^{-1}_G \bar{\phi}_G$ ), where the rank $n_G$ is significantly smaller than the matrix dimension $N_G$ . By combining this decomposition with the Woodbury identity, the authors reformulate the QTBM equation. This modification shifts the self-energy terms from the system matrix to the right-hand side injection vector. The resulting system matrix regains a structured sparsity pattern, becomes Hermitian, and is amenable to efficient block Gaussian elimination (specifically, a block Thomas algorithm).

Key Contributions

Extension of QTBM: The paper presents a novel extension of the QTBM framework capable of handling multi-terminal devices with large gate contacts at the ab initio level.
Algorithmic Efficiency: The combination of Bloch expansion and low-rank approximation reduces the computational complexity of OBC calculations and enables the solution of large, unstructured linear systems that were previously intractable.
First-Principles Application: The method is applied to a monolayer WS2 field-effect transistor (FET) with a 1.8 nm hBN dielectric and a Pt gate, utilizing Density Functional Theory (DFT) matrices generated by CP2K and processed by the open-source solver quatrex.

Results
The proposed method was validated and benchmarked on a WS2-hBN-Pt transistor structure:

Validation: Comparisons between the full-rank baseline, the low-rank approximation, and the combined Bloch expansion/low-rank approach for a gate length ( $L_g$ ) of 6.4 nm showed excellent agreement in drain-to-gate transmission functions, confirming the validity of the approximations.
Scalability: The method successfully simulated devices with gate lengths up to $L_g = 25.6$ nm. In contrast, treating the gate as a single full block limited simulations to $L_g \leq 12.8$ nm due to memory and time constraints.
Performance Gains:
- OBC Calculation: The Bloch expansion method provided speedups of up to 5.0 $\times$ and memory savings of up to 5.0 $\times$ for $L_g = 12.8$ nm compared to the full-cell approach.
- System Solution: The low-rank approximation, solved via a custom block Thomas algorithm, yielded runtime speedups of up to 7.8 $\times$ and memory savings of 2.8 $\times$ at $L_g = 22.4$ nm compared to the full-rank solver (cuDSS).
Physical Insights: The simulations revealed distinct peaks in source-to-gate and drain-to-gate transmission functions around 7.55 eV, corresponding to conduction band states in the WS2 channel. The drain-to-gate transmission was observed to be larger than the source-to-gate transmission, consistent with the steeper potential drop on the drain side.

Significance
The authors claim that this work enables the ab initio computation of gate leakage transmission functions for realistic nanoelectronic devices with 2D channels and gate lengths exceeding 25 nm. By overcoming the computational barriers associated with large gate contacts, this approach paves the way for investigating the influence of various dielectric layers on the leakage properties of ultra-scaled FETs, a capability previously unavailable in standard QT solvers.

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