H- SPICE Simulation of Graphene Nanoribbon Field-Effect Transistor Ternary Logic Gates: A Power-Delay Optimal Implementation of Multiple-Valued Logic Circuits

Technical Summary: H-SPICE Simulation of Graphene Nanoribbon Field-Effect Transistor Ternary Logic Gates

Problem Statement
The paper addresses the limitations of traditional binary logic in terms of information density and circuit complexity as device scaling reaches physical limits. While Multiple-Valued Logic (MVL), specifically ternary logic (base-3), offers a pathway to higher information density and simpler circuitry, its implementation requires robust transistor technologies that can support multiple logic states efficiently. The authors identify Graphene Nanoribbon Field-Effect Transistors (GNRFETs) as a promising alternative to Silicon and Carbon Nanotube FETs (CNTFETs) due to their tunable bandgap and high ON/OFF current ratios. However, there is a need for optimized ternary circuit designs using GNRFETs that demonstrate superior power-delay performance compared to existing CNTFET-based implementations.

Methodology
The study employs H-SPICE simulations using a 16 nm GNRFET model to design and analyze ternary logic circuits. The methodology involves:

1. Device Modeling: Utilizing Armchair Graphene Nanoribbons (AGNRs) where the electronic behavior is controlled by the number of dimer lines ($N$). The threshold voltage ($V_{th}$) is tuned by adjusting the ribbon width and dimer line count.
2. Circuit Design:
   • Standard Ternary Inverter (STI): A new design utilizing six GNRFETs (three n-type and three p-type) with specific dimer line configurations ($N=7, 9, 10$) to achieve distinct threshold voltages for logic levels 0, 1, and 2.
   • Ternary Decoder (TDECODER): A novel combinational circuit designed with only nine GNRFETs. It accepts one ternary input ($X$) and produces three binary outputs ($X_0, X_1, X_2$) corresponding to the input state.
3. Simulation Parameters: Simulations were conducted with a supply voltage ($V_{DD}$) of 0.95 V, an intermediate voltage of 0.45 V, a 50 ps input slew rate, and a 1 pF output load.
4. Comparative Analysis: The proposed GNRFET circuits were benchmarked against existing designs based on CNTFETs (referenced from literature [34, 35, 37, 42]) and other GNRFET models. The evaluation metrics included propagation delay, total power consumption, and Power-Delay Product (PDP).

Key Contributions

• Novel Circuit Architectures: The authors present a compact STI and a 9-transistor Ternary Decoder specifically optimized for GNRFET technology.
• Performance Optimization: The designs are engineered to minimize transistor count while maintaining high-speed operation and energy efficiency.
• Comprehensive Characterization: The paper provides a detailed analysis of the voltage transfer characteristics (VTC), noise margins (NM), and transient response of the proposed circuits.
• Quantitative Benchmarking: A direct comparison demonstrates that the proposed GNRFET-based designs outperform state-of-the-art CNTFET-based ternary logic gates in terms of delay and PDP.

Results
The H-SPICE simulation results indicate significant performance improvements for the proposed GNRFET circuits:

• Standard Ternary Inverter (STI): The proposed design achieves a delay of 0.38 ps and a PDP of $0.33 \times 10^{-18}$ J. This represents a substantial reduction in delay and PDP compared to existing CNTFET designs (e.g., CNTFET [34] shows 88.6 ps delay and 0.98 PDP).
• Ternary Decoder (TDECODER): The proposed 9-transistor decoder achieves a delay of 3.5 ps and a PDP of $0.03 \times 10^{-18}$ J.
• Comparative Metrics: When compared to state-of-the-art designs, the proposed GNRFET-based ternary decoder demonstrates a 2% reduction in delay and a 16% improvement in Power-Delay Product (PDP).
• Transistor Count: The proposed decoder uses 9 transistors, which is fewer than the 10–11 transistors required in comparable CNTFET or GNRFET designs found in the literature.

Significance and Claims
The paper claims that the proposed GNRFET-based ternary logic gates offer a "power-delay optimal implementation" for Multiple-Valued Logic circuits. The authors assert that these results highlight the "tremendous potential" of GNRFETs for creating high-performance, energy-efficient three-terminal logic circuits. The study concludes that such circuits are particularly suitable for future computing paradigms, specifically in low-power systems such as portable devices and embedded systems where energy conservation is critical. The work extends previous research by providing a unified approach to designing logic and computational circuitry based on GNRFETs, validating their superiority over traditional binary logic and existing carbon-based alternatives in the context of ternary logic.