⚡ electrical engineering

A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

This paper presents a fully tunable, ultra-low power, nine-transistor CMOS current-mode memory cell that enables robust bistable switching and serves as a versatile primitive for asynchronous spike-based logic gates and noise-immune recurrent units in neuromorphic computing.

Original authors: Arthur Fyon, Loris Mendolia, Jean-Michel Redouté, Alessio Franci, Guillaume Drion

Published 2026-05-11

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CC BY 4.0

Original authors: Arthur Fyon, Loris Mendolia, Jean-Michel Redouté, Alessio Franci, Guillaume Drion

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to build a super-efficient brain for a tiny, battery-powered device, like a smart sensor that needs to last for years without changing its batteries. The biggest problem with current computers is that they have to constantly move data back and forth between the "memory" (where information is stored) and the "processor" (where it is calculated). This is like a chef having to run back and forth to the pantry every time they need a pinch of salt; it wastes a huge amount of energy and time.

This paper introduces a new, tiny electronic component that solves this by combining memory and logic into a single, ultra-low-power switch. Here is how it works, explained through simple analogies:

1. The "Smart Door" (The Schmitt Trigger)

Think of the core invention as a smart door that doesn't just open when you push it; it remembers which way you pushed it last.

The Problem: Normal switches are fickle. If you push a door slightly, it might open a crack, then close, then open again if you wobble. It needs a constant push to stay open.
The Solution: This new "door" has a special memory. Once you push it hard enough to open it, it locks itself open. It stays open even if you let go. To close it, you have to push it in the opposite direction with a specific amount of force.
The "Hysteresis" (The Memory): This locking mechanism is called hysteresis. It creates a "dead zone" where small, accidental wobbles (noise) won't accidentally open or close the door. It only reacts to clear, deliberate pushes.

2. The "Water Flow" System (Current-Mode)

Most computer chips work with voltage (like water pressure). This new chip works with current (like the actual flow of water).

Imagine the chip is a system of pipes. Instead of measuring how hard the water is pushing, it counts how much water is flowing.
The authors built this using only nine tiny transistors (the microscopic switches inside a chip). It's like building a complex plumbing system with just nine pipes.
Because it uses such a tiny flow of water, it consumes almost no energy—so little that it operates in the nanowatt range. To put that in perspective, it uses about a billion times less power than a standard household lightbulb.

3. The "Three-Color" Code (Spike-Based Logic)

The authors figured out how to make this door do math by using a clever three-color code for water flow:

No Flow (0): Represents "Nothing happened yet" or a "Negative" signal.
Low Flow (Resting): Represents "Waiting."
High Flow (Spike): Represents a "Positive" signal.

Because the door remembers the last time it was pushed, it can perform logic operations (like AND, OR, XOR) just by looking at the direction of the last push.

Example: If you want an "AND" gate (which only says "Yes" if both inputs are positive), the system waits. If the last push on Input A was "High" and the last push on Input B was "High," the door opens. It doesn't matter if those pushes happened a second ago or a year ago; the door remembers the state until a new push arrives.

4. Why This Matters (The "Kitchen" Analogy)

In a normal computer, the memory and the brain are in different rooms. To solve a problem, the brain has to ask the memory for data, wait for it to arrive, solve the problem, and send the answer back. This is slow and wastes energy.

This new chip is like a kitchen where the chef and the pantry are the same person.

The "door" (the chip) holds the information (memory).
The "door" also decides what to do with that information (logic).
Because it remembers the last "spike" (event) indefinitely without needing to be refreshed, it can sit idle for years, consuming almost zero power, and instantly wake up to make a decision the moment a new event happens.

5. What the Paper Actually Says (The Limits)

The authors are very clear about what this chip can and cannot do:

It is Unipolar: It only works with "positive" water flow (current). It cannot handle negative currents directly, so they had to invent a clever coding system to simulate negative signals.
It is Slow (on purpose): The chip is designed for very slow, energy-efficient tasks (like monitoring a heartbeat or a temperature sensor), not for high-speed video processing. Its "speed limit" is about 1,000 operations per second, which is plenty for biological or environmental sensing but too slow for a smartphone.
It is Robust: The authors simulated this chip and found that even if the tiny components inside are slightly imperfect (which happens in real life), the "door" still works correctly and doesn't get confused by noise.

Summary

This paper presents a tiny, nine-transistor switch that acts as both a memory and a logic gate. It uses a "smart door" mechanism that remembers the last push it received, allowing it to perform calculations without needing to constantly refresh its memory. It runs on such low power that it is ideal for tiny, battery-free devices that need to "listen" to the world for years at a time, making decisions only when something interesting happens.

Technical Summary: A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

Problem Statement
The rapid expansion of edge computing and Internet-of-Things (IoT) applications necessitates hardware capable of performing inference and signal processing directly at sensor nodes with extreme energy efficiency. Conventional von Neumann architectures suffer from the "memory wall," where the physical separation of memory and processing units incurs significant energy and latency costs due to data movement. While in-memory computing offers a solution, existing approaches face distinct limitations:

Digital SRAM-based approaches: Require augmented bitcells for read stability and suffer from substantial area and power overhead from peripheral circuits (converters, sense amplifiers).
Memristive crossbar arrays: Offer high density but face challenges with device variability, programming nonlinearity, sneak path currents, and fabrication steps that often exceed standard CMOS processes.
Existing Schmitt Trigger designs: Prior voltage-mode implementations often rely on external resistors, fixed thresholds, or high power consumption. Current-mode designs, while compatible with subthreshold operation, typically lack full tunability of thresholds and hysteresis width or consume power in the microwatt ( $\mu$ W) range rather than the nanowatt (nW) range.

There is a specific gap for a pure CMOS primitive that combines bistable memory with ultra-low power operation, capable of performing logic on spikes over arbitrarily long time windows without refresh mechanisms or temporal constraints.

Methodology
The authors propose a novel, fully tunable, unipolar memory cell inspired by the Schmitt-trigger comparator, designed in a standard 180 nm CMOS process using only nine transistors. The circuit operates entirely in the current domain and utilizes a dual-Heaviside feedback structure:

Core Architecture: The design consists of two interdependent nonlinear thresholding elements.
- A primary Heaviside element activates when the input current ( $I_{in}$ ) exceeds a threshold ( $I_{thresh}$ ), producing an output current ( $I_{gain}$ ).
- A secondary Heaviside element is placed in a feedback loop, triggered by the output of the first stage. It injects a feedback current ( $I_{width}$ ) back into the input.
Bistability Mechanism: The feedback current lowers the effective input threshold to $I_{thresh} - I_{width}$ , creating a hysteresis loop. This ensures bistable switching behavior where the circuit retains its state until the input crosses the opposing threshold.
Tunability: Three key parameters are independently adjustable via programmable bias currents:
- $I_{thresh}$ : Controls the high switching threshold.
- $I_{width}$ : Controls the hysteresis width (and thus the low switching threshold).
- $I_{gain}$ : Controls the high-state output current.
Implementation: The circuit is resistorless and capacitorless, relying solely on standard MOSFET elements operating in the subthreshold regime. The design uses a conservative transistor sizing strategy (e.g., 5 $\mu$ m width) to mitigate mismatch and short-channel effects, prioritizing robustness and low power over high bandwidth (limited to ~1 kHz).

Key Contributions

Ultra-Low Power Current-Mode Schmitt Trigger: A nine-transistor implementation achieving power consumption in the nanowatt range (1 nW to 10 nW), significantly lower than prior current-mode designs (typically $\mu$ W to mW).
Full Independent Tunability: Unlike previous designs, this circuit allows independent control of the threshold current, hysteresis width, and output gain solely through bias currents.
Spike-Based Logic Family: The authors demonstrate a complete family of elementary logic gates (AND, OR, NAND, NOR, XOR) based on this memory cell. These gates utilize a three-level current encoding scheme (0 pA, 250 pA, 500 pA) to represent negative spikes, resting states, and positive spikes within a strictly positive current domain.
Persistent Memory without Refresh: The bistable nature of the cell allows it to retain the polarity of the last received spike indefinitely. This enables asynchronous logic operations that compare spike polarities without the need for temporal windowing or refresh circuits, a capability not previously demonstrated in pure CMOS spike-based logic.
Bistable Memory Recurrent Unit (BMRU): The circuit serves as the primitive for BMRUs in analog neural networks, where quantized hidden states provide inherent noise immunity.

Results
Simulations were conducted using SPICE with X-FAB 180 nm models at a 1.8 V supply:

Hysteresis and Stability: The circuit exhibits clear bistable behavior with sharp transitions. DC sweeps confirm two stable states with well-defined hysteresis.
Robustness: Monte Carlo analysis under 3 $\sigma$ process variation shows the circuit maintains correct switching behavior with only minor deviations (tens of pA) in thresholds and output levels. The design is also resilient to temperature variations, with typical operating conditions remaining well below 80°C.
Tunability: Systematic sweeps of bias currents confirm that $I_{gain}$ , $I_{thresh}$ , and $I_{width}$ control their respective parameters (output level, threshold, hysteresis width) in a linear and independent manner, with relative errors remaining low (e.g., < 6% at tested maximums).
Logic Operations: SPICE simulations of the five fundamental logic gates confirm correct functionality. The gates respond selectively to the polarity of the last spike on each input, with outputs persisting indefinitely until new spikes arrive. Power consumption for these gates remains in the tens of nW range.

Significance and Claims
The paper positions this design as a versatile building block for next-generation neuromorphic processors that integrate memory, logic, and recurrent computation.

Niche Occupancy: The design occupies a distinct niche between memristive approaches (high density but high variability/non-standard fabrication) and SRAM-based approaches (reliable but high area/power cost). It offers a pure CMOS implementation with nanowatt operation and persistent state retention.
Asynchronous Processing: By eliminating the need for temporal windowing, the circuit enables ultra-sparse, asynchronous event-driven processing where power is consumed only during spike transitions.
Hardware-Software Co-design: The authors note that this circuit has been employed in a hardware-software co-design demonstration for keyword spotting, achieving over 90% accuracy at ~100 nW power consumption, suggesting a potential three-order-of-magnitude improvement over comparable TinyML implementations.
Limitations: The authors explicitly acknowledge limitations, including unipolar operation (positive currents only) and a trade-off between operating frequency, transistor count/size, and power consumption. The current bandwidth is limited to approximately 1 kHz, which is suitable for biomedical and human-in-the-loop edge applications but not high-speed digital logic.

In summary, the work demonstrates that a compact, fully tunable, current-mode Schmitt trigger can serve as a fundamental primitive for ultra-low-power, asynchronous neuromorphic computing, overcoming the "memory wall" and the limitations of existing in-memory computing technologies through standard CMOS integration.